Following declaration of an array of struct, assumes size of byte, short, int and long are 1, 2, 3 and 4 respectively. Alignment rule stipulates that n-byte field must be located at an address divisible by n. The fields in a struct are not rearranged, padding is used to ensure alignment. All elements of array should be of same size.

Struct complx Short s Byte b Long l Int iEnd complxComplx C[10] 

Assuming C is located at an address divisible by 8, what is the total size of C, in Bytes ?
(A) 150
(B) 160
(C) 200
(D) 240

The Master theorem
(A) assumes the subproblems are unequal sizes
(B) can be used if the subproblems are of equal size
(C) cannot be used for divide and conquer algorithms
(D) cannot be used for asymptotic complexity analysis

Which of the following affects the processing power assuming they do not influence each other.

1. Data bus capability 1.
2. Addressing scheme
3. Clock speed 3.

(A) 3 only
(B) 1 and 3 only
(C) 2 and 3 only
(D) 1, 2 and 3

The immediate addressing mode can be used for

1. Loading internal registers with initial values 1.
2. Perform arithmetic or logical operation on data contained in instructions 2.

Which of the following is true ?
(A) Only 1
(B) Only 2
(C) Both 1 and 2
(D) Immediate mode refers to data in cache

If A = {x, y, z} and B = {u, v, w, x}, and the universe is {s, t, u, v, w, x, y, z}. Then (A U B’) ∩ (A ∩ B) is equal to
(A) {u, v, w, x}
(B) { }
(C) {u, v, w, x, y, z}
(D) {u, v, w}
(E) None of these

What is the in-order successor of 15 in the given binary search tree ?

(A) 18
(B) 6
(C) 17
(D) 2

The minimum height of an AVL tree with n nodes is
(A) Ceil (log₂ (n + 1))
(B) 1.44 log₂ n
(C) Floor (log₂ (n + 1))
(D) 1.64 log₂ n

A magnetic disk has 100 cylinders, each with 10 tracks of 10 sectors. If each sector contains 128 Bytes, what is the maximum capacity of the disk in kilobytes ?
(A) 1,280,000
(B) 1280
(C) 1250
(D) 128,000

A non-pipelined CPU has 12 general purpose registers (R0, R1, R2, ….. R12). Following operation are supported:

ADD Ra, Rb, Rr Add Ra to Rb and store the result in RrMUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr 

MUL operations takes two clock cycles, ADD takes one clock cycle.
Calculate minimum number of clock cycles required to compute the value of the expression XY + XYZ + YZ. The variables X, Y, Z are initially available in registers R0, R1 and R2 and contents of these registers must not be modified.
(A) 5
(B) 6
(C) 7
(D) 8

Which of the following is true ?
(A) Every subset of a regular set is regular
(B) Every finite subset of non-regular set is regular
(C) The union of two non-regular set is not regular
(D) Infinite union of finite set is regular