The Various types of delays in VHDL are :-

1. Delta delay - In VHDL simulations, all signal assignments occur with some infinitesimal delay, KNOWN as delta delay. VHDL uses the concept of delta delay to keep track of processes that should occur at a given time step,but are actually evaluated in different machine cycles .A delta delay is a unit of time as far as the simulator hardware is concerned, but in the simulation itself time has no advance. Technically, delta delay is of no measurable unit, but from a hardware design perspective one should think of delta delay as being the SMALLEST time unit one could measure, such as a femtosecond(fs).

2. Inertial delay - The inertial delay CAUSES the pulses less than specified delay to get suppressed & will not propogate these pulses to change the output. The inertial delay model is specified by ADDING an after clause to the signal assignment statement. Inertial delay is basically a default delay, i.e it's a component delay.

3. TRANSPORT delay - Tranport delay adds the propogation delay to the signal. The transport delay model just delays the change in the output by the time specified in the after clause. Transport delay basically represents a wire delay. 
e.g. q <=transport a nor b after 1ns ;

The Various types of delays in VHDL are :-

1. Delta delay - In VHDL simulations, all signal assignments occur with some infinitesimal delay, known as delta delay. VHDL uses the concept of delta delay to keep track of processes that should occur at a given time step,but are actually evaluated in different machine cycles .A delta delay is a unit of time as far as the simulator hardware is concerned, but in the simulation itself time has no advance. Technically, delta delay is of no measurable unit, but from a hardware design perspective one should think of delta delay as being the smallest time unit one could measure, such as a femtosecond(fs).

2. Inertial delay - The inertial delay causes the pulses less than specified delay to get suppressed & will not propogate these pulses to change the output. The inertial delay model is specified by adding an after clause to the signal assignment statement. Inertial delay is basically a default delay, i.e it's a component delay.

3. Transport delay - Tranport delay adds the propogation delay to the signal. The transport delay model just delays the change in the output by the time specified in the after clause. Transport delay basically represents a wire delay. 
e.g. q <=transport a nor b after 1ns ;