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Signal assignment is concurrent OUTSIDE the PROCESS and sequential WITHIN a process.

Signal assignment is concurrent outside the process and sequential within a process.

“ < = “.

“ < = “.

TYPE and Type ATTRIBUTES, VALUE, TIME.

Type and Type attributes, value, time.

We NEED FOLLOWING tools

1. SIMULATION tool.
2. Synthesis tool.
3. IMPLEMENTATION tool.

We need following tools

Sequential circuit uses flip FLOPS. Sequential circuits have STATE, which means basicallythey have memory. They COMPUTE the output based on INPUT and the state and updated basedon clocks. A combinational circuit does not have any STATES. They are functions of only inputs but not clocks. They are basically used to implement Boolean function.

Sequential circuit uses flip flops. Sequential circuits have state, which means basicallythey have memory. They compute the output based on input and the state and updated basedon clocks. A combinational circuit does not have any states. They are functions of only inputs but not clocks. They are basically used to implement Boolean function.

 Concurrent STATEMENTS will be USED in data FLOW level and SEQUENTIAL statements will beused in behavioral level.

 Concurrent statements will be used in data flow level and Sequential statements will beused in behavioral level.

DATA FLOW LEVEL, STRUCTURAL Level, BEHAVIORAL Level.

Data flow level, Structural Level, Behavioral Level.

in,out,INOUT,BUFFER.

in,out,inout,buffer.

SIGNALS are like a WIRES which connect design ENTITIES together and communicatechanges in values within a design.

Signals are like a wires which connect design entities together and communicatechanges in values within a design.

No, because FLOATING POINT NUMBERS cannot be MAPPED to HARDWARE.

No, because floating point numbers cannot be mapped to hardware.

SIGNAL, VARIABLE, CONSTANT.

Signal, Variable, Constant.

SCALAR TYPES and COMPOSITE Types.

Scalar Types and Composite Types.

ARRAY and RECORD.

Array and Record.

ARRAY contain MANY ELEMENTS of the same type. But RECORD CONTAINS many elements of different types.

Array contain many elements of the same type. But Record contains many elements of different types.

ALIAS is an ALTERNATIVE name assigned to part of an object. alias alias_name : SUBTYPE isname

Alias is an alternative name assigned to part of an object. alias alias_name : subtype isname

1. INERTIAL DELAY 
2. TRANSPORT delay.

USING after CLAUSE.

using after clause.

This is the DELAY OFTEN FOUND in switching circuits where spikes will not propogatefurther in circuit.

This is the delay often found in switching circuits where spikes will not propogatefurther in circuit.

Transport DELAY models the BEHAVIOR of a WIRE, in which all PULSES are propagatedirrespective there width.

Transport delay models the behavior of a wire, in which all pulses are propagatedirrespective there width.

DELTA DELAY.

delta delay.

1. std_logic_1164.
2. numeric_std.
3. numeric_bit.
4. std_logic_arith.
5. std_logic_unsigned.

Subtype is mainly USED for range checking and for IMPOSING ADDITIONAL constraints ONTYPES.

Subtype is mainly used for range checking and for imposing additional constraints ontypes.

D latch is a DEVICE it simply TRANSFERS data from input to OUTPUT when the ENABLE is activated.its used for the forming of d flip flops.

D latch is a device it simply transfers data from input to output when the enable is activated.its used for the forming of d flip flops.

Left SHIFT is equivalent to multiply operation and RIGHT shift is equivalent to divide operation. HENCE USING shift operations the same can be easily and efficiently IMPLEMENTED. 

Left shift is equivalent to multiply operation and right shift is equivalent to divide operation. Hence using shift operations the same can be easily and efficiently implemented. 

VERILOG and VHDL both are concurrent languages. Any hardware DESCRIPTIVE LANGUAGE is concurrent in nature.

Verilog and VHDL both are concurrent languages. Any hardware descriptive language is concurrent in nature.

Concurrent STATEMENTS define interconnected processes and blocks that together describe a DESIGN’s overall behavior or structure. They can be grouped using block statement. Groups of blocks can also be partitioned into other blocks. At the same level, a VHDL component can be connected to define signals within the blocks It is a reference to an entity A process can be a single signal assignment statement or a series of sequential statements (SS) Within a process, procedures and FUNCTIONS can partition the sequential statements.

Concurrent statements define interconnected processes and blocks that together describe a design’s overall behavior or structure. They can be grouped using block statement. Groups of blocks can also be partitioned into other blocks. At the same level, a VHDL component can be connected to define signals within the blocks It is a reference to an entity A process can be a single signal assignment statement or a series of sequential statements (SS) Within a process, procedures and functions can partition the sequential statements.

The Various types of delays in VHDL are :-

1. Delta delay - In VHDL simulations, all signal assignments occur with some infinitesimal delay, KNOWN as delta delay. VHDL uses the concept of delta delay to keep track of processes that should occur at a given time step,but are actually evaluated in different machine cycles .A delta delay is a unit of time as far as the simulator hardware is concerned, but in the simulation itself time has no advance. Technically, delta delay is of no measurable unit, but from a hardware design perspective one should think of delta delay as being the SMALLEST time unit one could measure, such as a femtosecond(fs).

2. Inertial delay - The inertial delay CAUSES the pulses less than specified delay to get suppressed & will not propogate these pulses to change the output. The inertial delay model is specified by ADDING an after clause to the signal assignment statement. Inertial delay is basically a default delay, i.e it's a component delay.

3. TRANSPORT delay - Tranport delay adds the propogation delay to the signal. The transport delay model just delays the change in the output by the time specified in the after clause. Transport delay basically represents a wire delay. 
e.g. q <=transport a nor b after 1ns ;

The Various types of delays in VHDL are :-

1. Delta delay - In VHDL simulations, all signal assignments occur with some infinitesimal delay, known as delta delay. VHDL uses the concept of delta delay to keep track of processes that should occur at a given time step,but are actually evaluated in different machine cycles .A delta delay is a unit of time as far as the simulator hardware is concerned, but in the simulation itself time has no advance. Technically, delta delay is of no measurable unit, but from a hardware design perspective one should think of delta delay as being the smallest time unit one could measure, such as a femtosecond(fs).

2. Inertial delay - The inertial delay causes the pulses less than specified delay to get suppressed & will not propogate these pulses to change the output. The inertial delay model is specified by adding an after clause to the signal assignment statement. Inertial delay is basically a default delay, i.e it's a component delay.

3. Transport delay - Tranport delay adds the propogation delay to the signal. The transport delay model just delays the change in the output by the time specified in the after clause. Transport delay basically represents a wire delay. 
e.g. q <=transport a nor b after 1ns ;

The VHDL language can be used for SEVERAL goals like -

1. To SYNTHESIZE digital circuits.
2. To VERIFY and validate digital designs.
3. To generate test vectors to test circuits.
4. To SIMULATE circuits.

The VHDL language can be used for several goals like -

VHDL stands for "VHSIC Hardware DESCRIPTION Language." VHSIC, in TURN, stands for "Very High Speed INTEGRATED CIRCUIT," which was a U.S. Department of Defense program.

VHDL stands for "VHSIC Hardware Description Language." VHSIC, in turn, stands for "Very High Speed Integrated Circuit," which was a U.S. Department of Defense program.