Concurrent STATEMENTS define interconnected processes and blocks that together describe a DESIGN’s overall behavior or structure. They can be grouped using block statement. Groups of blocks can also be partitioned into other blocks. At the same level, a VHDL component can be connected to define signals within the blocks It is a reference to an entity A process can be a single signal assignment statement or a series of sequential statements (SS) Within a process, procedures and FUNCTIONS can partition the sequential statements.

Concurrent statements define interconnected processes and blocks that together describe a design’s overall behavior or structure. They can be grouped using block statement. Groups of blocks can also be partitioned into other blocks. At the same level, a VHDL component can be connected to define signals within the blocks It is a reference to an entity A process can be a single signal assignment statement or a series of sequential statements (SS) Within a process, procedures and functions can partition the sequential statements.