In virtually all computers nowadays we use Dynamic Random Access Memory (DRAM) for our main volatile storage and Static Random Access Memory (SRAM) as a cache memory for higher speed memory reading/writing built into the CPU.

So why don't we use SRAM in place of DRAM and free up space in our processors?

I already know that SRAM is more expensive but by how much? Surely enthusiasts would pay many dollars for even faster RAM and CPU designers would be happy to have more space to work with.As you said, it's more expensive. It's about 6 times the price for SRAM of the same capacity as DRAM. Of course, that only applies where SRAM can actually be manufactured in the same size. Die size for SRAM also grows quite large at higher capacities. It also CONSUMES far more power.

If SRAM were used as the main memory of a PC, aside from the higher cost, the RAM that get's installed would be large enough that cases would need to be designed specifically to hold each SRAM Shelf that get's installed. Each SRAM shelf would need an effective cooling solution, equivalent to perhaps the air-channel-cowling used on graphics cards to keep the SRAM cool. It would also require a much more powerful power supply than is typically found in a PC.

it simply isn't worth the requirement to re-engineer a standard to accomodate RAM shelves rather than RAM sticks, and the added price of the power usage and cooling to use the higher speed SRAM as main memory.

Also much of the performance advantage from SRAM on the CPU die itself is a result of literally being physically close to the processor core. If the CPU had to reach across the bus for every memory access, it wouldn't matter how fast the memory is because the distance would impair performance below what the on-chip cache's currently have, and since a large majority of CPU memory access is able to access cached data acquired from main memory via the prefetcher, it would likely result in a net slowdown in performance.I like the reply by BC.

The OP may have an erroneous idea. The CPU will  generate a refresh for the RAM at regular intervals. This has been a built-in feature from the early days** . It would do nothing to make the CPU  smaller, faster, sexy or anything.

Perhaps the OP received his training in the no shoelace school. At that place  teachers taught students not to have shoelaces because it was a waste of time. 

** The Intel 8080 did not have refresh, but the Zilog Z-80  did.Geek-9pm, I have no formal computer training (aside from a laughable ICT GCSE from my school days). WIKIPEDIA is my friend. Quote from: Geek-9pm on May 10, 2016, 02:05:18 PM

The OP may have an erroneous idea. The CPU will  generate a refresh for the RAM at regular intervals. This has been a built-in feature from the early days** . It would do nothing to make the CPU  smaller, faster, sexy or anything.
Perhaps the OP received his training in the no shoelace school. At that place  teachers taught students not to have shoelaces because it was a waste of time. 

This paper INTRODUCES a novel ultra-low-power SRAM. A large power reduction is obtained by the use of four new techniques that allow for a wider and better trade-off between area, delay and active and passive energy consumption for low-power embedded SRAMs. The design targets wireless applications that require a moderate performance at an ultra-low-power consumption. The implemented design techniques consist of a more efficient memory databus, the exploitation of the dynamic read stability of SRAM cells, a new low-swing write technique and a distributed decoder. An 8-KB 5T SRAM was fabricated in a 0.18-mum technology. The measurement results confirm the feasibility and the usefulness of the proposed techniques. A reduction of active power consumption with a factor of 2 is reported as compared to the current state of the art. The results are generalized towards a 32-KB SRAM.