Some of the benefits of using UVM are:

• Modularity and Reusability – The methodology is designed as modular components (Driver, Sequencer, Agents , env etc) which enables REUSING components across unit level to multi-unit or chip level verification as well as across projects.
• Separating Tests from Test benches – Tests in terms of stimulus/sequencers are kept SEPARATE from the actual test bench hierarchy and hence there can be REUSE of stimulus across different units or across projects.
• Simulator independent – The base class library and the methodology is supported by all simulators and hence there is no dependence on any specific simulator.
• BETTER control on Stimulus generation – Sequence methodology gives good control on stimulus generation. There are several ways in which sequences can be developed which includes randomization, layered sequences, virtual sequences etc which provides a good control and rich stimulus generation capability.
• Easy configuration – Config mechanisms simplify configuration of objects with deep hierarchy. The configuration mechanism helps in easily configuring different test bench components based on which verification environment uses it and without worrying about how deep any component is in test bench hierarchy.
• Factory mechanism – Factory mechanisms simplifies modification of components easily. Creating each components using factory enables them to be overridden in different tests or environments without changing underlying code base.

Some of the benefits of using UVM are: