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InterviewSolution
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What Is Uvm Ral Model? Why It Is Required? |
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Answer» In a VERIFICATION context, a register model (or register abstraction layer) is a set of CLASSES that model the memory mapped BEHAVIOR of registers and memories in the DUST in order to facilitate stimulus generation and functional checking (and optionally some ASPECTS of functional coverage). The UVM provides a set of base classes that can be extended to implement COMPREHENSIVE register modeling capabilities. In a verification context, a register model (or register abstraction layer) is a set of classes that model the memory mapped behavior of registers and memories in the DUST in order to facilitate stimulus generation and functional checking (and optionally some aspects of functional coverage). The UVM provides a set of base classes that can be extended to implement comprehensive register modeling capabilities. |
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