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The CORRECT choice is (C) UNIVERSITY of Berkeley

Easy explanation: The University of Berkeley and Stanford university provides the basic architecture model of RISC.

The CORRECT choice is (b) 8

The best explanation: The 8087 coprocessor does not have a main REGISTER set but they have an 8-level deep STACK register from st0 to st7.

The correct choice is (a) MC6800

Easiest EXPLANATION: MC6800 is the first microprocessor by Motorola which STARTED a revolution in the embedded SYSTEMS.

Correct CHOICE is (c) SUPERSCALAR

The BEST I can explain: Superscalar architecture support out-of-order execution in which the instructions later in the STREAM are executed before EARLIER instructions.

Correct answer is (a) VLIW

To explain I would say: VLIW is a very long instruction word which receives many instructions and is executed in one instructed word. VLIW is majorly designed for instruction-level parallel (ILP) that is, it can execute codes concurrently or parallel in some time. TTA is a transport triggered architecture which is a TYPE of CPU design which programs CONTROLLING the INTERNAL buses of the processor. Test-and-set is USED to write to a memory location and return its old values. ALU used to perform arithmetic and logic operations.

Right answer is (a) JOSH Fisher

For explanation: Josh Fisher from Yale Universities INVENTED the concept of VLIW architecture. John Ellis described the VLIW compiler. John Ruttenberg develops some important algorithms in SCHEDULING.

The correct OPTION is (d) trap base register

The best EXPLANATION: The trap vector table is located in the trap base register which supplies the ADDRESS of the service routine. When it is completed REIT INSTRUCTIONS are executed.

The correct answer is (a) register windowing

For explanation I would SAY: SPARC follows Berkeley architecture MODEL and uses register windowing in order to improve the context SWITCHING and parameter passing. It ALSO SUPPORTS superscalar operations.

The correct choice is (a) multiply accumulator

The EXPLANATION is: When MAC instruction is EXECUTED, the two of the 24-bit ADDITIONAL REGISTERS are multiplied together and then added or subtracted from A and B. It takes place in a single machine cycle of 75ns at 27MHz.

Right CHOICE is (b) NMI and INTR

To explain: The 80386 has two external interrupt signals which allow external devices to interrupt the processor. The INTR input CREATES a maskable interrupt while the NMI creates a non-maskable interrupt.

Correct choice is (a) CONTROL unit and numeric control unit

To elaborate: Control unit interfaces the coprocessor with its MAIN microprocessor whereas numeric control unit can EXECUTE the coprocessor instructions.

The correct choice is (B) 24

Best EXPLANATION: The SIZE of the address bus in 80286 is 24 bits and 20 bits in 8088 and 8086.

The correct option is (B) ESCAPE instruction

Easiest explanation: When 8086 COMES ACROSS any floating point arithmetic operations, it EXECUTES ESCAPE instruction code in ORDER to pass the control of bus and instruction op-code to 8087.

The correct answer is (a) Multicore architecture

The explanation is: The Multicore machine is a combination of MANY processors on a single chip. The HETEROGENEOUS multicore machine ALSO combines AVARIETY of processor TYPES on a single chip.

Right option is (c) 80386

Easiest explanation: The instruction SET is same as that of 80386 but there are some additional INSTRUCTIONS available when the PROCESSOR is in PROTECTED MODE.

Right choice is (b) 2’s complement

Explanation: In a COPROCESSOR, negative NUMBERS are stored in 2’s complement with its leftmost sign bit of 1 WHEREAS positive numbers are stored in the form of TRUE value with its leftmost sign bit of 0.

The CORRECT CHOICE is (a) 40 PIN DIP

The best I can explain: All 8087 models have a 40 pin DIP which is operated in 5V.

Correct choice is (c) In protected mode

For EXPLANATION: In protected mode, two ADDITIONAL register ARISES which is called index register and base pointer register which HELPS in EXPANDING the register.

Correct option is (b) 8086 and 80286

For EXPLANATION: 80286 is BASED on the ARCHITECTURE of 8086. So both the processors have the same set of INSTRUCTIONS with SLIGHT variations.

Right OPTION is (a) 8

The EXPLANATION: MC6800 POSSESSES an 8-bit accumulator register since it is an 8-bit processor.

Right CHOICE is (a) SPARC

To ELABORATE: The BERKELEY RISC design was developed between the year 1980 and 1984 and later on the RISC design were commercialized as SPARC processor.

Right OPTION is (d) ARM9E

To explain I would say: ARM9E can also have DSP LEVEL of PERFORMANCE without having a digital signal processor by its enhanced DSP instructions.

Right option is (a) Harvard

Easiest explanation: Harvard architecture in a digital SIGNAL processor allows CONTINUOUS data FETCHING and PERFORMING the CORRESPONDING instructions.

The correct ANSWER is (b) AX,BX,CX,DX

The best I can explain: Intel 80286 POSSESS 4 general purpose registers and these are 16-bit in size. In addition to the general purpose register, there are four SEGMENTED registers, two INDEX registers and a base POINTER register.

Correct answer is (d) On-chip paging memory management unit

The EXPLANATION is: Because of the efficient paging mechanism of 80386 in the memory management unit, it SUPPORTS multitasking which MEANS DIFFERENT tasks can be done at a time, a kind of parallel execution.