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• It is one of the most IMPORTANT 8 BIT register of 8085
• It is responsible for coordinating input and output to and from the MICROPROCESSOR through it.
• The primary purpose of this register is to store temporary data and for the placement of FINAL values of arithmetic and logical operations.
• This accumulator register is mainly used for arithmetic, logical, store and rotate operations.

1. The Stack pointer is a sixteen bit register used to point at the stack.
2. In read WRITE memory the locations at which temporary data and return addresses are stored is KNOWN as the stack.
3. In simple words stack acts LIKE an auto DECREMENT facility in the system.
4. The initialization of the stack top is done with the help of an instruction LXI SP.
5. In order to avoid program crashes a program should always be WRITTEN at one end and initialized at the other.

1. The flag register in 8085 is an 8-bit register which contains 5 bit positions.
2. These five flags are of 1BIT F/F and are known as zero, sign, carry, PARITY and auxiliary carry.
3. For sign flag if the result of an MSB operation is 1 then it is set else it is RESET.
4. The zero flag is set of the result of an instruction is zero.
5. The auxiliary carry flag is used for BCD operations, not FREE to the programmer.
6. The carry flag is used for carrying and borrowing in case of addition and subtraction operations.
7. The parity flag is used for results containing an even number of one's.

• The timing and control circuitry SECTION of the 8085 is responsible for the generation of timing and control signals so that instructions can be executed.
• The TYPES of signals involved are : Clock signals, Control signals, Status signals, DMA signals and also the reset section.
• It is responsible for the fetching and the decoding of the various operations.
• This section also aids in the generations of control signals for the executions of instructions and for the SYNC between external DEVICES.

1. If there are more general purpose registers the program writing process is more FLEXIBLE and convenient.
2. The NUMBER of BITS that would be required to detect the registers would INCREASE with more registers, this results in the lowering of the number of OPERATIONS.
3. When a program would involve CALL subroutines the status of the registers would have to be saved and restored often, this would result in a significant overhead for the processor.
4. Higher the number of these registers mores space would be used by them on the chip. This can create problems in adding / implementing other functions on the chip.

1. The WAIT state plays a significant role in preventing CPU speed incompatibilities.
2. Many a TIMES the processor is at a ready state to accept data from a device or location, but there might be no input available. This can lead to wastage of cpu time.
3. So in such cases when the cpu is ready for an input but there is no such VALID data then the system gets into WAIT state. In this SCENARIO the PIN 35 ( ready pin )is put into a low state.
4. As SOON as there is some valid data for the 8085 the system comes off the WAIT state and the low state of the READY pin is withdrawn.

Fetch cycle is the TIME required to fetch an opcode from a particular location in memory.

1. General Fetch Cycles CONSIST of 3T states.
2. The first T state involves the sending of the memory address STORED in the Program Counter to the memory.
3. During the second T state the contents of the addressed memory is read ( this generally is the opcode at the specified location)
4. In the third T state the opcode is sent to the INSTRUCTION register through the data bus for execution.
5. For slower MEMORIES the processors has the provision to get in to the WAIT cycles as well.

Fetch cycle is the time required to fetch an opcode from a particular location in memory.

The flow of a typical Instruction word is as FOLLOWS:

1. The content of the program counter of 2 byte is transferred to the address register known as MAR ( MEMORY address register ). This occurs at the starting of a fetch CYCLE.
2. The contents are transferred VIA the address bus.
3. Once this is done the timing and control section of the processor reads the contents of the referenced memory address location.
4. After this the data is sent to the memory data register with the help of the data bus.
5. Now the data is placed in the instruction register which will eventually decode and execute it.

The flow of a typical Instruction word is as follows:

YES the 8085 does support several externally initiated operations. The possible operations and the corresponding PINS for them in the 8085 are as follows:

1. It supports resetting ( this is possible with the Reset Pin ).
2. Various interruptions ( these are possible through Trap, RST 7.5, 6.5, 5.5 and the interrupt pins. )
3. The 8085 also supports Readying with the HELP pf the READY pin.
4. It also has a HOLD pin which can basically pause the operation till required/ as required.

Yes the 8085 does support several externally initiated operations. The possible operations and the corresponding pins for them in the 8085 are as follows:

1. The HOLD is a hardware INPUT WHEREAS HLT is a software INSTRUCTION.
2. When the HLT state is executed the processor simply stops and the buses are driven to tri state. No form of acknowledgement signal is given out by the processor.
3. In case of HOLD the processor goes into hold state but the buses are not driven to tri state.
4. When the processor goes into the HOLD state it gives out an HLDA signal. This signal can be made to use by other devices.

The various TYPES of data transfer operations possible are:

• Data transfer is possible between two registers.
• It is also possible between a MEMORY location and a register.
• Also it can occur between an input/output device and an accumulator.
• In reality data is NEVER TRANSFERRED it can only be copied from ONE location to another.

The various types of data transfer operations possible are:

The various types of ADDRESSING modes of the 8085 are as follows:

1. Direct addressing: The INSTRUCTIONS in itself CONTAIN the opearand. For ex. STA5513H or in/out instructions such as IN PORT C.
2. Register addressing: The general purpose registers contain the operands. For ex. MOV A, B;
3. Register indirect addressing: This involves the use of register PAIRS instead of a single register. For ex MOV A, M; ADD M.
4. Immediate addressing: The example are MVI A, 07; or ADI 0F etc.
5. Implicit addressing: this FORM of addressing contains no operands. For ex. RAR, CMA etc.

The various types of addressing modes of the 8085 are as follows:

The INTR is a maskable INTERRUPT for the 8085. It has the lowest priority and is also non vectored. When this INTR signal goes into the high state the following things occur / take place:

1. For every instruction that is executed the 8085 checks the status of this interrupt./
2. Till an instruction is completed the signal of INTR will remain high. Once an instruction is completed the processor sends an acknowledgement signal INTA.
3. As soon as the INTA signal goes low a new OPCODE is PLACED on the data bus for transfer.
4. Once the new instruction is received the processor saves the ADDRESS of new instruction into the STACK and an interrupt service subroutine begins.

The INTR is a maskable interrupt for the 8085. It has the lowest priority and is also non vectored. When this INTR signal goes into the high state the following things occur / take place:

1. The TRAP input is SENSITIVE to both EDGE and level.
2. The pulse width for this signal should be in excess as compared to the normal noise width.
3. A SECOND trap will never be able to respond for the second time as it requires the first trap to go through a high to low transition.
4. The pulse widths are wider than normal widths so as to prevent unwanted FALSE TRIGGERS.

The two major differences between INTR and the other hardware INTERRUPTS are as follows:

• All the hardware interrupts are vectored interrupts but the INTR interrupt is not so. An INTR interrupt will ALWAYS get the address of a SUBROUTINE from the device ( external ) itself. In the case of other hardware interrupts the interrupts come from the call generated by the processor at a already determined vector location.
• In case of the INTR interrupt the RETURN address of an interrupt is never saved but in the case of other hardware interrupts the locations is saved in the STACK.

The two major differences between INTR and the other hardware interrupts are as follows:

On the BASIS of level the signals can be classified into the following types:

• Single level interrupts
• Multi level interrupts
• The differences between them are as follows:
• For single the interrupts are manages through a single PING whereas in multi they are MANAGED by multiple pins.
• For single level interrupts polling is essential whereas for multi level it is not necessary.
• Single level interrupts are MUCH SLOWER than multi level interrupts.

On the basis of level the signals can be classified into the following types:

By making use of the Push & Pop INSTRUCTIONS the PROGRAM can be written as:

• LXISP, 4000H - this step initiates the SP at 4000h.
• PUSH PSW - the contents of the accumulator and flag are PUSHED into the stack.
• POP B 
• MOV A, B
• STA 2000H
• MOV A, C
• STA 2001H
• HLT

By making use of the Push & Pop instructions the program can be written as:

The steps followed in this type of TRANSFER are as follows:

• The PERIPHERAL device would request for an interrupt.
• The request acknowledgement for the transfer is issued at the end of INSTRUCTION execution.
• Now the ISS routine is initialized, The PC has the return ADDRESS which is now stored in the stack.
• Now data transfer is managed and coordinates by the ISS.
• Again the Interrupt system is enabled and the above steps are repeated.

The steps followed in this type of transfer are as follows:

The VARIOUS functional blocks of the 8085 microprocessor are:

• Registers 
• Arithmetic logic unit 
• ADDRESS BUFFER 
• Increment / decrement address LATCH 
• Interrupt control 
• Serial I/O control 
• Timing and control circuitry 
• Instructions decoder and machine cycle encoder.

The various functional blocks of the 8085 microprocessor are:

The SIGNALS of the 8085 microprocessor based on their functions can be classified into 7 categories namely:

• Frequency and POWER signals
• Address and DATA buses
• The control bus
• Interrupt Signals
• Serial Input / OUTPUT signals
• DMA signals
• RESET Signals

The signals of the 8085 microprocessor based on their functions can be classified into 7 categories namely:

RST 6.5 & RST 5.5 are level-triggering INTERRUPTS

RST 6.5 & RST 5.5 are level-triggering interrupts

The QUALITY factor is also defined, as Q. So it is a number, which REFLECTS the lossness of a circuit. Higher the Q, the lower are the losses.

The Quality factor is also defined, as Q. So it is a number, which reflects the lossness of a circuit. Higher the Q, the lower are the losses.

Because of high stability, LARGE Q (Quality Factor) & the frequency that doesn’t DRIFT with AGING. Crystal is used as a clock source most of the TIMES.

Because of high stability, large Q (Quality Factor) & the frequency that doesn’t drift with aging. Crystal is used as a clock source most of the times.

Yes, it can be used, if an accurate clock frequency is not required. Also, the component cost is low compared to LC or CRYSTAL.

Yes, it can be used, if an accurate clock frequency is not required. Also, the component cost is low compared to LC or Crystal.

KEYBOARDS, Floppy disk are the EXAMPLES of INPUT devices. PRINTER, LED / LCD display, CRT Monitor are the examples of OUTPUT devices.

Keyboards, Floppy disk are the examples of input devices. Printer, LED / LCD display, CRT Monitor are the examples of output devices.

Flag is called as LOW ORDER register & Accumulator is called as HIGH order Register.

Flag is called as Low order register & Accumulator is called as High order Register.

There are 12 INTERRUPTS in 8085.

There are 12 interrupts in 8085.

Immediate, DIRECT, REGISTER, Register INDIRECT, Implied addressing MODES.

Immediate, Direct, Register, Register indirect, Implied addressing modes.

TRAP has the HIGHEST PRIORITY.

TRAP has the highest priority.

RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7.

RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7.

TRAP, RST7.5, RST6.5, RST5.5, INTR.

TRAP, RST7.5, RST6.5, RST5.5, INTR.

In 8085 the INTERRUPTS are CLASSIFIED as HARDWARE and SOFTWARE interrupts.

In 8085 the interrupts are classified as Hardware and Software interrupts.

8085 is a ONE ADDRESS MICROPROCESSOR.

8085 is a one address microprocessor.

A bus is a GROUP of conducting lines that CARRIERS data, address, & control SIGNALS.

A bus is a group of conducting lines that carriers data, address, & control signals.

The MICRO PROCESSOR ENTERS into Halt-State and the BUSES are tri-stated.

The Micro Processor enters into Halt-State and the buses are tri-stated.

LIFO (LAST In First Out) STACK is used in 8085.In this TYPE of Stack the last stored INFORMATION can be retrieved first.

LIFO (Last In First Out) stack is used in 8085.In this type of Stack the last stored information can be retrieved first.

Sign FLAG, ZERO flag, AUXILLARY flag, Parity flag, CARRY flag.

Sign flag, Zero flag, Auxillary flag, Parity flag, Carry flag.

ACCUMULATOR register, Temporary register, Instruction register, STACK Pointer, PROGRAM Counter are the various registers in 8085.

Accumulator register, Temporary register, Instruction register, Stack Pointer, Program Counter are the various registers in 8085.