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SIM is Set INTERRUPT Mask. Used to mask the hardware interrupts. RIM is Read Interrupt Mask. Used to check whether the interrupt is MASKED or not.

SIM is Set Interrupt Mask. Used to mask the hardware interrupts. RIM is Read Interrupt Mask. Used to check whether the interrupt is Masked or not.

FIFO (First In First Out) STACK is used in 8086.In this type of Stack the first stored INFORMATION is RETRIEVED first.

FIFO (First In First Out) stack is used in 8086.In this type of Stack the first stored information is retrieved first.

In 8086 CARRY flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag.

basically there r two types of interrupti.e.internal and EXTERNAL INTERRUPTS.internal interrupts are software inetrrupts which can maskable or nonmaskable where as external interrupts are DUE to some hardware reset,and are non maskable.

In 8086 Carry flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag.

basically there r two types of interrupti.e.internal and external interrupts.internal interrupts are software inetrrupts which can maskable or nonmaskable where as external interrupts are due to some hardware reset,and are non maskable.

Maskable INTERRUPTS, Non-Maskable interrupts.

Maskable interrupts, Non-Maskable interrupts.

An INTERRUPT which can be NEVER be TURNED off (ie.disabled) is KNOWN as Non-Maskable interrupt.

An interrupt which can be never be turned off (ie.disabled) is known as Non-Maskable interrupt.

Non-Maskable interrupts are used in critical EVENTS. Such as Power FAILURE, Emergency, SHUT off ETC.

Non-Maskable interrupts are used in critical events. Such as Power failure, Emergency, Shut off etc.

RST 7.5, RST6.5, RST5.5 are Maskable INTERRUPTS.

RST 7.5, RST6.5, RST5.5 are Maskable interrupts.

TRAP is KNOWN as Non-Maskable INTERRUPTS, which is used in EMERGENCY CONDITION.

5MHZ

Trap is known as Non-Maskable interrupts, which is used in emergency condition.

5MHZ

memory is divided into TWO bank:

1:EVEN bank
2:ODD bank.

memory is divided into two bank:

1:even bank
2:odd bank.

8086 has a SPECIAL CONCEPT CALLED as memory segmentation.It allows parallel processing, while 8085 does not.

8086 has a special concept called as memory segmentation.It allows parallel processing, while 8085 does not.

memory SIZE of 8086 is 1MB memory size of 8085 is 64KB 2 ^(adresslines)=size of memory (bytes) so adress LINES of 8086 are 20 and 8085 is 16

memory size of 8086 is 1MB memory size of 8085 is 64KB 2 ^(adresslines)=size of memory (bytes) so adress lines of 8086 are 20 and 8085 is 16

8086 is used for general purpose like it is used in traffic signals for control purpose .It’s ALSO used for SMALL APPLICATIONS like for calculator,etc

SCIENTIFIC calculators & small arithmatic operations

8086 is used for general purpose like it is used in traffic signals for control purpose .It’s also used for small applications like for calculator,etc

scientific calculators & small arithmatic operations

8086 is having 2 different units i.e. BIU(Bus Interface UNIT) and EU(EXECUTION Unit), these two units work synchronously.

8086 is having 2 different units i.e. BIU(Bus Interface Unit) and EU(Execution Unit), these two units work synchronously.

INTERPRETER is the TOOL USED to CONNECT the USER and the tool.

Interpreter is the tool used to connect the user and the tool.

The address line is 02 LESS than the EARLIER VALUE. Decrement by 2.

The address line is 02 less than the earlier value. Decrement by 2.

The ADDRESS line is 02 GREATER than the EARLIER VALUE.

The address line is 02 greater than the earlier value.

Accumulator is the REGISTER in which ARITHMETIC and Logic CALCULATIONS are done.

Accumulator is the register in which Arithmetic and Logic calculations are done.

A program runs on one machine and EXECUTES on another is CALLED as CROSS-COMPILER

Programs which compile on One Machine and Execute on Another machine is called cross compiler.

A program runs on one machine and executes on another is called as cross-compiler

Programs which compile on One Machine and Execute on Another machine is called cross compiler.

Stack Segment in segment REGISTER is used to store INTERRUPT and subroutine RETURN address REGISTERS.

Stack Segment in segment register is used to store interrupt and subroutine return address registers.

1. TRACE FLAG,
2. INTERRUPT Flag,
3. DIRECTION Flag.

Basically,8086 is divided into two PART. 1.BIU. 2.EU EXECUTION UNIT(EU)Fetch the intruction from Queue(memory(6 byte) in BIU.) and EXECUTE it.

Basically,8086 is divided into two part. 1.BIU. 2.EU Execution Unit(EU)Fetch the intruction from Queue(memory(6 byte) in BIU.) and execute it.

FREQUENCY HOPPING is the TECHNOLOGY USED in BLUETOOTH.

Frequency hopping is the technology used in Bluetooth.

The EU goes into the WAIT mode in the following three conditions:

1. If an instruction requires an access to a MEMORY location which is not present in the queue the EU enters into the WAIT state.
2. The EU enters into the WAIT mode when a JUMP instruction is executed. In such CASES the EXISTING queue contents are removed the EU waits for more instructions from the new address in the memory.
3. Certain instructions can take quite some time to execute in such cases the EU again goes into the WAIT state. For cases such as these the BIU waits till the EU is able to EXTRACT some bytes from the queue.

The EU goes into the WAIT mode in the following three conditions:

The 8086 in total CONSISTS of 14 16 bit registers. They are grouped together in the following WAY:

1. All the registers are DIVIDED into the following groups: Data, Pointers and Index group, segment group and status and control flag group.
2. The accumulator AX, base BX, count CX and data DX ACCOUNT for the data registers.
3. The stack pointer SP, base pointer BP, source index SI, Destination index DI and the Instruction painter IP are the pointer registers.
4. The Extra segment, code segment and stack segment are in the segment group of registers
5. A single 16 bit flag register is present in the Control flag group.

The 8086 in total consists of 14 16 bit registers. They are grouped together in the following way:

Some of the advantages of memory segmentation in the 8086 are as follows:

1. With the help of memory segmentation a user is able to work with registers having only 16-bits. 
2. By memory segmentation the various portions of a PROGRAM can be of more than 68kb.
3. The data and the USERS code can be stored separately allowing for more flexibility.
4. Also DUE to segmentation the logical address range is from 0000H to FFFFH the code can be LOADED at any LOCATION in the memory.

Some of the advantages of memory segmentation in the 8086 are as follows:

1. Logical address is contained in the 16-bit IP, BP, SP, BX, SI or DI. It is also known as the offset address or the effective address.
2. The BASE segment address is contained in one of the 16bit contents of the segment registers CS, DS, ES, SS.
3. The physical address or the real address is formed by combining the offset and base segment addresses. This address is 20bit and is PRIMARILY used for the accessing of the memory.

The following are the different types of instructions:

1. Move byte or word instructions: they are used to perform primarily the move function on words / bytes
2. Exchange byte or word instructions: as their name suggests they are used to perform exchange OPERATIONS
3. Translate byte instructions: used for TRANSFER PURPOSES.
4. Load effective address instructions: used to CALCULATE the effective address and load it to memory.
5. Load DATA segment instructions: used for loading purposes.
6. Load extra segment instructions: used for special instructions such as span etc.

The following are the different types of instructions:

The various characteristics of the Compare (CMP) instruction are as follows:

1. The CMP instruction can be used to compare TWO 8-bit or two 16-bit numbers.
2. Whenever a compare operation is performed the result of such an operation reflects in one of the six status flags CF, AF, OF, PF, SF and ZF.
3. The CMP operation is also known as the subtraction method as it uses two`s COMPLEMENT for it.
4. The result of a CMP operation is never saved but corresponding to the result of the instruction the flag statuses may be changed or RESET.
5. The operands of CMP instruction may reside in the MEMORY or can be a component of an instruction.

The various characteristics of the Compare (CMP) instruction are as follows:

The characteristics of Short Label instructions are:

• This type of INSTRUCTION relative to the jump instruction ADDRESS specifies the jump.
• The new value of an IP is specified with an 8-bit operand.
• From the LOCATION of the jump instruction the range in which this instruction can be used is between -126 to +129 bytes.

The characteristics of Near Label instructions are as follows:

• For Near label instruction the address of the jump is specified in relative terms to the jump instruction itself.
• The new VALUES of Ip is specified with a sixteen-bit operand.
• This type of instruction covers the complete range of the code segment currently used.

The characteristics of Short Label instructions are:

The characteristics of Near Label instructions are as follows:

The CHARACTERISTICS of NMI are as follows:

• They are also known as the non-maskable types.
• They are always give higher priorities over the INTR.
• The interrupt is edge triggered specifically Low to High transition.
• In order to function they must remain high for at LEAST 2 cycles of CLK.
• These INTERRUPTS do not send out any form of ACKNOWLEDGEMENTS.

The characteristics of INTR are:

• They are also known as the maskable types of interrupts.
• They have a lower priority as compared to NMI.
• These interrupts are level triggered and not edge triggered.
• These interrupts do not support latching and must remain high till the CPU acknowledges them to do so.

The characteristics of NMI are as follows:

The characteristics of INTR are:

The FOLLOWING steps occur when an interrupt occurs ( both for hardware and software ):

1. First thing the contents of the flag register the CS and IP are pushed into the stack.
2. To disable the single steps and INTR interrupts the TF and IF are cleared.
3. The program then JUMPS to the beginning or starting address of the ISS.
4. When the IRET gets executed in the last line ( this occurs at the end of the ISS) the CS and IP flag contents are popped from the stack and PLACED in the appropriate registers.
5. Once all the flags are restored to their original condition the IF and TF are ALSO restored to their previous VALUES.

The following steps occur when an interrupt occurs ( both for hardware and software ):

The following would be the code:

• 2000 CLD : Clears the direction flag
• 2001 MOV SI, 4000 H : In the SI the STORE ADDRESS is placed
• 2004 MOV DI, 5000 H : In the DI the destination address is put
• 2007 MOV CX, 0064 H : In the CX the number of bytes to be 2`s complemented are placed
• 200A LODSB : The data byte is give to AL and INC SI
• 200B NEGAL : AL of 2`s complement.
• 200D STOSB : Current AL value into DI and INC DI
• 200E LOOPNZ 200A H : The loop is maintained till CX becomes = 0.
• 2010 HLT : Stop.

The following would be the code:

The characteristics of isolated I/O are as follows:

1. The devices of I/O are TREATED in a separate DOMAIN as compared to MEMORY.
2. A total of 1mb address space is allowed for memory applications.
3. In order to maximize the I/O operations ( isolated ) separate instructions are always provided to perform these operations.
4. One of the disadvantages is that the data transfer only occurs between the I/O port and the AL, AX registers.

The characteristics of the memory mapped I/O are as follows:

1. In such scenarios the devices (I/O) are treated as a part of the memory only.
2. Complete 1mb of memory cannot be used as they are a part of the memory.
3. In case of memory mapped I/O operations no external separate instructions are required.
4. There is data transfer restriction in case of memory mapped instructions.

The characteristics of isolated I/O are as follows:

The characteristics of the memory mapped I/O are as follows:

Some of the characteristics of internal interrupts are as follows:

1. The type of code of an interrupt is either predefined or can be contained within the instruction itself.
2. In case of INTR interrupt INPUTS the generation of complementary INTA bus cycles are not generated.
3. No internal interrupt can be DISABLED in the case of such interrupts barring single STEP interrupts.
4. PRIORITY Wise always the internal interrupts barring single step interrupts are always given higher priority as compared to external interrupts.

Some of the characteristics of internal interrupts are as follows:

The following are the various types of interrupts:

1. Type 0 interrupts: This interrupt is ALSO known as the divide by zero interrupt. For CASES where the quotient becomes particularly large to be PLACED / ADJUSTED an error might occur.
2. Type 1 interrupts: This is also known as the single step interrupt. This type of interrupt is primarily used for debugging purposes in assembly language.
3. Type 2 interrupts: also known as the non-maskable NMI interrupts. These type of interrupts are used for emergency scenarios such as power failure.
4. Type 3 interrupts: These type of interrupts are also known as breakpoint interrupts. When this interrupt occurs a PROGRAM would execute up to its break point.
5. Type 4 interrupts: Also known as overflow interrupts is generally existent after an arithmetic operation was performed.

The following are the various types of interrupts:

1. The 8086 has THREE control FLAGS namely TF, IF and DF. All three of them can be user programmed to suit their needs.
2. The trap flag allows the cpu to run in a SINGLE stepping mode. This comes in very handy in debugging and DEVELOPMENT purposes.
3. The interrupt flag causes the INTR ( maskable interrupt ) to be enabled else it would remain disabled. Whenever the cpu is reset so is IF reset / cleared.
4. In string operations primarily the Direction flag is used. The STD instruction is responsible for the setting of the DF.

1. Stack pointer and base pointer are the TWO pointer REGISTERS whereas the Source index and DESTINATION index are the index group of registers.
2. They are primarily used to store relative to segment registers the LOCATIONS of offset addresses of MEMORY locations. They serve the purpose of being memory pointers.
3. The source index and destination index are also used as general purpose register. In such cases the SI and DI are implemented as source and destination index registers.
4. In stacks, data areas might exist, to be able to access such data which contains the BP register.

Features of the 8086:

• A DATA width of 2 byte is attained by the de multiplexing of AD0 to AF15 PINS.
• The INSTRUCTION queue is of 6 bytes.
• From the memory the fetching of a program is performed only once there are 2 byte empty in queue.
• The BIU of 8086 is not as same as in the 8088 but the EU is similar.

Features of the 8088:

1. It requires a 1 byte data width which is generated after the de multiplexing of AD0 to AD7 pins.
2. The instruction queue is 4-bytes.
3. Program fetching is performed as soon as there is a byte empty in queue.

Features of the 8086:

Features of the 8088:

The arithmetic operations in the 8086 can be CATEGORIZED as follows:

1. Data TRANSFER instructions: These types of instructions involve transfer data using commands such as MOV etc.
2. Arithmetic instructions: As their name suggest these instructions are used to perform arithmetic operations for ex. ADD, SUB etc. 
3. Logic instructions: Performs special logical gate operations ex NOT OPR etc.
4. Shift instructions: Used for shift operations in special conditions ex. SHL, SHR.
5. Rotate instructions: They are used to rotate left, right ex. ROL, ROR.
6. FLAG control instructions: They are used to configure the various flags such as: STC, CLC, CMC, STD etc.
7. Compare instructions: As their name suggests they are used to perform compare operations
8. Jump instructions: Used to perform the Jump Operations
9. Subroutines and subroutine handling instructions: Primarily are used for interrupt handlings ex. IRET, INT etc.
10. Loop and loop handling instructions: Used to handle loop operations
11. Strings and string handling instructions: Performed solely on strings.

The arithmetic operations in the 8086 can be categorized as follows:

1. The TWO types of unconditional jumps are intersegment and intrasegment jumps.
2. In the case of intrasegment jumps as the name suggest is a special type of jump in which the ADDRESS to which the jump is to be performed is present / lies in the same code segment from where the jump is performed from. In order to perform this jump changes just need to be made in the Instruction POINTER.
3. In the case of intersegment jumps the jump TAKES place from one segment to another. In order to be ABLE to make these kinds of jumps the changes need to be made in both the code segment and the instruction pointer.

The advantages of using modular programming techniques are as follows:

1. By using a modular programming approach the user is able to USE macros, macros are sections of CODE which execute in one go upon being ACTIVATED. These macros can be reused throughout the program.
2. The use of modular programming TECHNIQUE also helps the user to use subroutines these can also be considered to be procedures which can provide GREATER control over the functioning.
3. By using this approach the data that is used can be structured and can be globally accessed by other modules whoever requires it.

The advantages of using modular programming techniques are as follows:

The functions PERFORMED by the Bus interface unit are:

• The BIU is responsible for the external bus operations.
• It performs fetching, reading, writing for memory as well as I/O of data for peripheral devices.
• The BIU also performs address generation and the population of the instruction queue.

The Execution unit is responsible for the following work:

1. The instructions are decoded and executed by it.
2. The EU ACCEPTS instructions from the instruction queue and from the GENERAL purpose registers it TAKES data.
3. It has no relation with the system buses.

The functions performed by the Bus interface unit are:

The Execution unit is responsible for the following work: