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The correct CHOICE is (B) JTAG

The explanation: The JTAG is a technique for connecting scan chains of SEVERAL chips and is ALSO known as boundary scan.

Right CHOICE is (a) computational tree logic

To explain I would say: The EMC-system is a popular system for MODEL checking which is developed by Clark that describes the CTL formulas, which is also known as computational tree LOGICS. The CTL consist of two PARTS, a path quantifier, and a state quantifier.

Right choice is (b) fault TREE analysis

For explanation: The FTA is also KNOWN as the Fault tree analysis which is a top-down method of analyzing RISKS. The analysis starts with damage and COMES up with the reasons for the damage. The analysis can be checked graphically by using GATES.

The correct choice is (B) test PATTERN

Easiest explanation: The test pattern GENERATION is normally based on the fault models and this model is also known as the stuck-at model. The test pattern is based on a certain assumption, that is why it is CALLED the stuck-at model.

The CORRECT choice is (d) failure mode and EFFECT analysis

To explain I WOULD SAY: The FMEA is the failure mode and the effect analysis, in which the analysis STARTS at the components and tries to estimate their reliability.

The correct CHOICE is (c) AND

Explanation: The fault tree analysis is DONE graphically by using gates. The MAIN gates used are AND gates and OR gates. The AND gates are used in the graphical representation if several events CAUSE hazards.

Right CHOICE is (a) switch-level MODEL

The BEST I can explain: The switch model can be used in the simulation of the transistors since the transistor is the very basic component in a switch. It is capable of REFLECTING bidirectional transferring of the information.

The correct option is (B) finite state machine

Explanation: The FSM is the finite state machine. It will be having a finite NUMBER of states and is used to design both the sequential logic circuit and the computer PROGRAMS. It can be used for TESTING the scan design in the testing techniques.

Right option is (c) Propositional logic

Easy explanation: The propositional logic technique is having the boolean formulas and the boolean function. The TOOLS used in propositional logic is the tautology checker or the equivalence checker which in TURN USES the binary decision diagrams which are ALSO known as BDD.

The correct choice is (b) binary DECISION diagrams

Easy EXPLANATION: The binary decision DIAGRAM is a kind of data structure which is USED to represent the Boolean function.

The CORRECT option is (d) cyclic REDUNDANCY check

For explanation: The CRC or the cyclic redundancy check is the error detecting code which is commonly USED in the storage device and the digital NETWORKS.

The CORRECT option is (C) DESIGN for testability

Easiest explanation: The design of testability or DfT is the PROCESS of designing for the better testability.

Correct option is (c) TEST pattern

For explanation I would say: For testing any devices or embedded systems, we use some SORT of selected inputs which is known as the test pattern and observe the output and is COMPARED with the EXPECTED output. These test patterns are normally applied to the manufactured systems.

Correct answer is (B) FTA

To explain I would say: The FTA is DONE graphically by using gates mainly AND gates and OR gates. The OR GATE is used to REPRESENT the single event which is hazardous.

Correct answer is (c) BDD

Best EXPLANATION: The model CHECKING was developed USING the binary decision diagram and the BDD and it was possible to locate ERRORS in the specification of the future bus PROTOCOL.

Correct ANSWER is (a) fault coverage

The explanation is: The quality of the test pattern can be EVALUATED on the BASIS of the fault coverage. It is the percentage of potential FAULTS that can be found for a given test pattern set, that is fault coverage equals the NUMBER of detectable faults for a given test pattern set divided by the number of faults possible due to the fault model.

The correct answer is (a) higher ORDER LOGIC

Best explanation: The formal verification TECHNIQUES are classified on the basis of the LOGICS employed. The techniques are propositional logic, first order logic, and higher order logic. The HOL is the abbreviation of the higher order logic in which the proofs are automated and MANUALLY done with some proof support.

The CORRECT answer is (a) scan design

Best EXPLANATION: All the flip-flop storing STATES are connected to FORM a shift REGISTER in the scan design. It is a kind of test path.

Right option is (d) EMC

The explanation: The EMC-system is developed by CLARK and it DESCRIBES the CTL formulas, which is the computational TREE logics.

Right option is (d) first ORDER logic

For EXPLANATION I would SAY: MANY formal verification techniques are USED and these are classified on the basis of the logics employed. The techniques are propositional logic, first order logic, and higher order logic. The FOL is the abbreviated form of the first order logic which includes the quantification.

Correct ANSWER is (C) fine-grained model

To ELABORATE: The fine-grained model has the cycle-true instruction set SIMULATION. In this modelling, it is possible to compute the EXACT number of clock cycles which is required to run an application.

The correct choice is (d) test PATTERN

The best I can explain: The test pattern generation is basically based on the fault MODELS and this TYPE of MODEL is also known as the stuck-at model. These test patterns are based on a CERTAIN assumption, hence it is known as the stuck-at model.

The correct ANSWER is (a) test pattern

The explanation is: While testing any devices or embedded systems, we APPLY some selected inputs which is known as the test pattern and OBSERVE the output. This output is compared with the expected output. The test patterns are normally APPLIED to the already manufactured systems.