An instruction pipeline has 4 stages Instruction Fetch(IF), Instruction Decode(ID), Execute instruction (Ex), Write Back(WB). All instructions take all stages and takes 4 clock cycles. Branch instructions are not overlapped, i.e. the instructions after the branch are not fetched till branch is known. Branch is known in the execute phase. Suppose 20 % instructions are conditional and 80 % unconditional. Calculate speed up for 100 instructions (upto 2 decimal place). Ignore the case that the branch may not be taken.(A) 2.86(B) 3.21(C) 1.65(D) 2.57

An instruction pipeline has 4 stages Instruction Fetch(IF), Instructio

1.	An instruction pipeline has 4 stages Instruction Fetch(IF), Instruction Decode(ID), Execute instruction (Ex), Write Back(WB). All instructions take all stages and takes 4 clock cycles. Branch instructions are not overlapped, i.e. the instructions after the branch are not fetched till branch is known. Branch is known in the execute phase. Suppose 20 % instructions are conditional and 80 % unconditional. Calculate speed up for 100 instructions (upto 2 decimal place). Ignore the case that the branch may not be taken.(A) 2.86(B) 3.21(C) 1.65(D) 2.57
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