Can A Master Change The Address/control Signals During A Waited Trans

1.	Can A Master Change The Address/control Signals During A Waited Transfer?
Answer» YES. If the address/control signals are indicating an IDLE TRANSFER then the master can CHANGE to a real transfer (NONSEQ) when HREADY is low. However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response. Yes. If the address/control signals are indicating an IDLE transfer then the master can change to a real transfer (NONSEQ) when HREADY is low. However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response.

Can A Master Change The Address/control Signals During A Waited Transfer?

Answer»

YES. If the address/control signals are indicating an IDLE TRANSFER then the master can CHANGE to a real transfer (NONSEQ) when HREADY is low.

However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response.

Yes. If the address/control signals are indicating an IDLE transfer then the master can change to a real transfer (NONSEQ) when HREADY is low.

However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response.

Discussion

No Comment Found

Related InterviewSolutions

What Is The Difference Between Split And Retry Responses?
Can A Slave Use Both Split And Retry Responses?
Do All Slaves Have To Support The Split And Retry Responses?
Can A Slave Assert Hsplitx In The Same Cycle That It Gives A Split Response?
Will A Master Always Lose The Bus After A Split Response?
Can A Split Or Retry Response Be Given At Any Point During A Burst?
Do All Masters Have To Support Split And Retry?
What Address Should Be On The Bus During The Idle Cycle After A Split Or Retry?
What Value Should Be Used For Htrans When An Ahb Master Gets A Retry Response From A Slave In The Middle Of Burst?
How Should Ahb To Apb Bridges Handle Accesses That Are Not 32-bits?