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Can A Master Deassert Hlock During A Burst? |
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Answer» The AHB specification requires that all ADDRESS PHASE timed control SIGNALS (other than HADDR and HTRANS) REMAIN constant for the duration of a BURST. Although HLOCK is not an address phase timed signal, it does directly control the HMASTLOCK signal which is address phase timed. Therefore HLOCK must remain high for the duration of a burst, and can only be deasserted such that the following HMASTLOCK signal changes after the final address phase of the burst. The AHB specification requires that all address phase timed control signals (other than HADDR and HTRANS) remain constant for the duration of a burst. Although HLOCK is not an address phase timed signal, it does directly control the HMASTLOCK signal which is address phase timed. Therefore HLOCK must remain high for the duration of a burst, and can only be deasserted such that the following HMASTLOCK signal changes after the final address phase of the burst. |
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