How Do You Implement The Bi-directional Ports In Verilog Hdl?

1.	How Do You Implement The Bi-directional Ports In Verilog Hdl?
Answer» module bidirec (OE, clk, INP, outp, bidir); // Port DECLARATION input oe; input clk; input [7:0] inp; output [7:0] outp; INOUT [7:0] bidir; reg [7:0] a; reg [7:0] B; assign bidir = oe ? a : 8'bZ ; assign outp = b; // Always Construct always @ (posedge clk) begin b <= bidir; a <= inp; end endmodule module bidirec (oe, clk, inp, outp, bidir); // Port Declaration input oe; input clk; input [7:0] inp; output [7:0] outp; inout [7:0] bidir; reg [7:0] a; reg [7:0] b; assign bidir = oe ? a : 8'bZ ; assign outp = b; // Always Construct always @ (posedge clk) begin b <= bidir; a <= inp; end endmodule

Answer»

module bidirec (OE, clk, INP, outp, bidir);

input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
INOUT [7:0] bidir;
reg [7:0] a;
reg [7:0] B;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;

// Always Construct

always @ (posedge clk)

begin
b <= bidir;
a <= inp;
end
endmodule

module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration

input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;

// Always Construct

always @ (posedge clk)

begin
b <= bidir;
a <= inp;
end
endmodule

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