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Is It Possible To Reduce Clock Skew To Zero? Explain Your Answer? |
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Answer» Even though there are clock layout strategies (H-tree) that can in THEORY reduce clock SKEW to zero by having the same path length from each flip-flop from the pll, process variations in R and C across the chip will cause clock skew as WELL as a pure H-Tree scheme is not practical (consumes too much area). Even though there are clock layout strategies (H-tree) that can in theory reduce clock skew to zero by having the same path length from each flip-flop from the pll, process variations in R and C across the chip will cause clock skew as well as a pure H-Tree scheme is not practical (consumes too much area). |
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