Execution of blocking assignments can be viewed as a one-step process:

1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement. A blocking assignment "blocks" TRAILING assignments in the same always block from occurring until after the current assignment has been completed 

Execution of nonblocking assignments can be viewed as a two-step process: 

1. Evaluate the RHS of nonblocking statements at the beginning of the TIME step.
2. Update the LHS of nonblocking statements at the end of the time step. 

Execution of blocking assignments can be viewed as a one-step process:

1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement. A blocking assignment "blocks" trailing assignments in the same always block from occurring until after the current assignment has been completed 

Execution of nonblocking assignments can be viewed as a two-step process: