Timing jitter can be reduced by(a) Good power supply isolation(b) Stable clock reference(c) Good power supply isolation & Stable clock reference(d) None of the mentionedThis question was addressed to me in final exam.My doubt is from Sources of Corruption topic in section Formatting and Baseband Modulation of Digital Communications

Timing jitter can be reduced by(a) Good power supply isolation(b) Stab

1.	Timing jitter can be reduced by(a) Good power supply isolation(b) Stable clock reference(c) Good power supply isolation & Stable clock reference(d) None of the mentionedThis question was addressed to me in final exam.My doubt is from Sources of Corruption topic in section Formatting and Baseband Modulation of Digital Communications
Answer» The CORRECT ANSWER is (c) Good POWER supply isolation & Stable clock reference For explanation: Jitter occurs when there is a slight POSITION change in the sampled signals. This timing jitter can be controlled by power supply isolation and clock reference.

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