In circuit design, clock skew is a phenomenon in SYNCHRONOUS circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.

This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or SLOWER than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit’s size) arrive at different PARTS of the circuit at different times. Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flipflop to a destination flipflop. If the destination flipflop receives the clock tick later than the source flipflop, and if the logic path delay is short enough, then the data signal might arrive at the destination flipflop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flipflop to be properly clocked through. If the destination flipflop receives the clock tick earlier than the source flipflop, then the data signal has that much less time to reach the destination flipflop before the next clock tick. If it fails to do so, a setup violation occurs, socalled because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period at which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this linear program, zero clock skew is merely a feasible point.

Clock skew can be minimized by proper routing of clock signal (clock DISTRIBUTION tree) or putting variable delay BUFFER so that all clock inputs arrive at the same time.

In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.

This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit’s size) arrive at different parts of the circuit at different times. Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flipflop to a destination flipflop. If the destination flipflop receives the clock tick later than the source flipflop, and if the logic path delay is short enough, then the data signal might arrive at the destination flipflop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flipflop to be properly clocked through. If the destination flipflop receives the clock tick earlier than the source flipflop, then the data signal has that much less time to reach the destination flipflop before the next clock tick. If it fails to do so, a setup violation occurs, socalled because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period at which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this linear program, zero clock skew is merely a feasible point.

Clock skew can be minimized by proper routing of clock signal (clock distribution tree) or putting variable delay buffer so that all clock inputs arrive at the same time.