For an undefined length burst (INCR) a master must KEEP its HBUSREQ signal asserted until it has started the address phase of the LAST transfer in the burst. This will MEAN that if the penultimate transfer in the burst is zero wait state then the master may be granted the bus for an additional transfer at the end of an undefined length burst.

For a defined length burst the master can deassert the HBUSREQ signal once the master has been granted the bus for the first transfer. This can be done because the ARBITER is able to count the transfers in the burst and keep the master granted until the burst completes.

However it is not a mandatory requirement for an Arbiter to allow a burst to complete, so the master will have to re-assert HBUSREQ if the Arbiter removes HGRANT before the burst has been completed.

For an undefined length burst (INCR) a master must keep its HBUSREQ signal asserted until it has started the address phase of the last transfer in the burst. This will mean that if the penultimate transfer in the burst is zero wait state then the master may be granted the bus for an additional transfer at the end of an undefined length burst.

For a defined length burst the master can deassert the HBUSREQ signal once the master has been granted the bus for the first transfer. This can be done because the arbiter is able to count the transfers in the burst and keep the master granted until the burst completes.

However it is not a mandatory requirement for an Arbiter to allow a burst to complete, so the master will have to re-assert HBUSREQ if the Arbiter removes HGRANT before the burst has been completed.