<P>NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three TIMES that of holes COMPARED to NOR and thus the NAND is a faster gate.

Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more SYMMETRIC in case of NAND ( the delay profile), but for NOR, one delay is much higher than the other(OBVIOUSLY t_plh is higher since the higher resistance p mos's are in series connection which again increases the resistance).

NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate.

Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance p mos's are in series connection which again increases the resistance).