Will Case Infer Priority Register If Yes How Give An Example?

1.	Will Case Infer Priority Register If Yes How Give An Example?
Answer» yes case can INFER priority register DEPENDING on CODING style reg r; // Priority encoded mux, ALWAYS @ (a or b or C or select2) begin r = c; case (select2) 2'b00: r = a; 2'b01: r = b; endcase end yes case can infer priority register depending on coding style reg r; // Priority encoded mux, always @ (a or b or c or select2) begin r = c; case (select2) 2'b00: r = a; 2'b01: r = b; endcase end

Answer»

yes case can INFER priority register DEPENDING on CODING style
reg r;
// Priority encoded mux,
ALWAYS @ (a or b or C or select2)
begin
r = c;
case (select2)
2'b00: r = a;
2'b01: r = b;
endcase
end

yes case can infer priority register depending on coding style
reg r;
// Priority encoded mux,
always @ (a or b or c or select2)
begin
r = c;
case (select2)
2'b00: r = a;
2'b01: r = b;
endcase
end

Discussion

No Comment Found

Related InterviewSolutions

What Are Different Types Of Verilog Simulators ?
Why Is It That "if (2'b01 & 2'b10)..." Doesn't Run The True Case?
What Is Verilog Case (1) ?
How Do You Implement The Bi-directional Ports In Verilog Hdl?
What Is The Difference Between Wire And Reg?
How To Generate Sine Wav Using Verilog Coding Style?
What Is The Difference Between === And == ?
What Does `timescale 1 Ns/ 1 Ps Signify In A Verilog Code?
What Is The Difference Between The Following Two Lines Of Verilog Code?
Given The Following Verilog Code, What Value Of "a" Is Displayed?

Will Case Infer Priority Register If Yes How Give An Example?

Discussion

No Comment Found

Related InterviewSolutions

Reply to Comment