Write A Verilog Code For Synchronous And Asynchronous Reset?

1.	Write A Verilog Code For Synchronous And Asynchronous Reset?
Answer» Synchronous reset, synchronous means clock dependent so reset MUST not be present in sensitivity DISK eg: ALWAYS @ (POSEDGE clk ) begin if (reset) . . . end Asynchronous means clock INDEPENDENT so reset must be present in sensitivity list. Eg: Always @(posedge clock or posedge reset) begin if (reset) . . . end Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg: always @ (posedge clk ) begin if (reset) . . . end Asynchronous means clock independent so reset must be present in sensitivity list. Eg: Always @(posedge clock or posedge reset) begin if (reset) . . . end

Answer»

Synchronous reset, synchronous means clock dependent so reset MUST not be present in sensitivity DISK

eg: ALWAYS @ (POSEDGE clk )

begin if (reset)
. . . end

Asynchronous means clock INDEPENDENT so reset must be present in sensitivity list.

Eg: Always @(posedge clock or posedge reset)

begin
if (reset)
. . . end

Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk

eg: always @ (posedge clk )

begin if (reset)
. . . end

Asynchronous means clock independent so reset must be present in sensitivity list.

Eg: Always @(posedge clock or posedge reset)

begin
if (reset)
. . . end

Discussion