54 + Interview Questions in Arithmetic in Computer Architecture Page 1 InterviewSolution

1.	Out of the following which is not a CISC machine.(a) IBM 370/168(b) VAX 11/780(c) Intel 80486(d) Motorola A567The question was posed to me in an interview for internship.The query is from CISC and RISC Processors topic in chapter Arithmetic of Computer Architecture
Answer» CORRECT CHOICE is (d) MOTOROLA A567 Explanation: NONE.

Discussion

2.	In super-scalar processors, ________ mode of execution is used.(a) In-order(b) Post order(c) Out of order(d) None of the mentionedI had been asked this question in final exam.I'm obligated to ask this question of Superscalar Processors topic in section Arithmetic of Computer Architecture
Answer» CORRECT answer is (c) Out of order To explain I WOULD say: It follows out of order EXECUTION to speed up the execution of instructions.

Discussion

3.	The throughput of a super scalar processor is _______(a) less than 1(b) 1(c) More than 1(d) Not KnownThis question was posed to me by my school principal while I was bunking the class.My question is based upon Superscalar Processors in chapter Arithmetic of Computer Architecture
Answer» CORRECT option is (C) More than 1 For EXPLANATION: The throughput of a processor is measured by using the number of instructions executed PER second.

Discussion

4.	The logic operations are simpler to implement using logic circuits.(a) True(b) FalseI had been asked this question during an interview.My query is from Fast Adders topic in division Arithmetic of Computer Architecture
Answer» Right option is (a) True Explanation: The LOGIC OPERATION includes AND, OR, XOR etc.

Discussion

5.	The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________(a) Half adders(b) Full adders(c) Ripple adders(d) Fast addersI have been asked this question in exam.My question is taken from Fast Adders topic in division Arithmetic of Computer Architecture
Answer» The CORRECT CHOICE is (b) Full adders For EXPLANATION: In this the carry for the next step is generated in the previous steps operation.

Discussion

6.	The contention for the usage of a hardware device is called ______(a) Structural hazard(b) Stalk(c) Deadlock(d) None of the mentionedI had been asked this question by my college director while I was bunking the class.Question is taken from Pipe-lining topic in division Arithmetic of Computer Architecture
Answer» The CORRECT ANSWER is (a) STRUCTURAL hazard Explanation: NONE.

Discussion

7.	The pipelining process is also called as ______(a) Superscalar operation(b) Assembly line operation(c) Von Neumann cycle(d) None of the mentionedThe question was asked in my homework.Asked question is from Pipe-lining in chapter Arithmetic of Computer Architecture
Answer» CORRECT choice is (b) Assembly LINE operation For EXPLANATION: It is called so because it PERFORMS its operation at the assembly level.

Discussion

8.	The product of -13 & 11 is ______________(a) 1100110011(b) 1101110001(c) 1010101010(d) 1111111000I got this question in final exam.This interesting question is from Multiplication topic in portion Arithmetic of Computer Architecture
Answer» CORRECT CHOICE is (b) 1101110001 The best explanation: NONE.

Discussion

9.	The multiplier is stored in ______(a) PC Register(b) Shift register(c) Cache(d) None of the mentionedI got this question during an interview.This is a very interesting question from Multiplication topic in portion Arithmetic of Computer Architecture
Answer» CORRECT option is (b) SHIFT REGISTER Best EXPLANATION: The value is stored in a shift register so that each bit can be ACCESSED separately.

Discussion

10.	The normalized representation of 0.0010110 * 29 is _______(a) 0 10001000 0010110(b) 0 10000101 0110(c) 0 10101010 1110(d) 0 11110100 11100I had been asked this question in a job interview.I want to ask this question from Representation of Floating Number in portion Arithmetic of Computer Architecture
Answer» Correct option is (b) 0 10000101 0110 For EXPLANATION I WOULD say: NORMALIZED REPRESENTATION is done by SHIFTING the decimal point.

Discussion

11.	When the processor executes multiple instructions at a time it is said to use _______(a) single issue(b) Multiplicity(c) Visualization(d) Multiple issuesThe question was asked during an online exam.My query is from Superscalar Processors in chapter Arithmetic of Computer Architecture
Answer» Correct option is (d) MULTIPLE issues To explain I WOULD SAY: None.

Discussion

12.	In super-scalar mode, all the similar instructions are grouped and executed together.(a) True(b) FalseThis question was posed to me in quiz.My enquiry is from Superscalar Processors in portion Arithmetic of Computer Architecture
Answer» RIGHT choice is (a) True To ELABORATE: The instructions are GROUPED meaning that the instructions FETCH and decode and other cycles are OVERLAPPED.

Discussion

13.	Both the CISC and RISC architectures have been developed to reduce the ______(a) Cost(b) Time delay(c) Semantic gap(d) All of the mentionedThis question was posed to me during an interview for a job.My question is from CISC and RISC Processors in section Arithmetic of Computer Architecture
Answer» Right OPTION is (c) Semantic GAP To EXPLAIN: The semantic gap is the gap between the high level language and the LOW level language.

Discussion

14.	________ constitute the representation of the floating number.(a) Sign(b) Significant digits(c) Scale factor(d) All of the mentionedThe question was posed to me in unit test.My question is based upon Representation of Floating Number topic in portion Arithmetic of Computer Architecture
Answer» Right OPTION is (d) All of the mentioned The BEST explanation: The following FACTORS are RESPONSIBLE for the REPRESENTATION of the number.

Discussion

15.	If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have ______(a) Exception handling(b) Imprecise exceptions(c) Error correction(d) None of the mentionedThis question was posed to me by my school principal while I was bunking the class.I need to ask this question from Superscalar Processors topic in section Arithmetic of Computer Architecture
Answer» Right answer is (b) IMPRECISE exceptions For explanation: The processor SINCE as executed the FOLLOWING INSTRUCTIONS EVEN though an exception was raised, hence the exception is treated as imprecise.

Discussion

16.	The 32 bit representation of the decimal number is called as ___________(a) Double-precision(b) Single-precision(c) Extended format(d) None of the mentionedThis question was posed to me during an internship interview.This question is from Representation of Floating Number topic in portion Arithmetic of Computer Architecture
Answer» Right CHOICE is (B) Single-precision To EXPLAIN I would say: NONE.

Discussion

17.	The multiplier -6(11010) is recorded as _______(a) 0-1-2(b) 0-1+1-10(c) -2-10(d) None of the mentionedThe question was posed to me in unit test.The query is from Multiplication topic in chapter Arithmetic of Computer Architecture
Answer» The CORRECT OPTION is (a) 0-1-2 To EXPLAIN: NONE.

Discussion

18.	The final addition sum of the numbers, 0110 & 0110 is ____________(a) 1101(b) 1111(c) 1001(d) 1010The question was asked in an online interview.This intriguing question comes from Fast Adders in chapter Arithmetic of Computer Architecture
Answer» RIGHT OPTION is (a) 1101 Explanation: NONE.

Discussion

19.	The usual implementation of the carry circuit involves _________(a) And & or gates(b) XOR(c) NAND(d) XNORThe question was posed to me in an online interview.My question is taken from Fast Adders topic in division Arithmetic of Computer Architecture
Answer» The correct OPTION is (b) XOR The best I can explain: In CASE of full and half adders this METHOD is used.

Discussion

20.	Each stage in pipelining should be completed within ___________ cycle.(a) 1(b) 2(c) 3(d) 4This question was addressed to me in class test.Question is taken from Pipe-lining topic in division Arithmetic of Computer Architecture
Answer» The correct option is (a) 1 To ELABORATE: The stages in the PIPELINING should get completed within ONE cycle to increase the SPEED of PERFORMANCE.

Discussion

21.	The numbers written to the power of 10 in the representation of decimal numbers are called as _____(a) Height factors(b) Size factors(c) Scale factors(d) None of the mentionedThis question was posed to me in an online quiz.My query is from Representation of Floating Number topic in division Arithmetic of Computer Architecture
Answer» CORRECT option is (c) Scale FACTORS Easy explanation: These are called as scale factors CAUSE they’re responsible in determining the degree of specification of a NUMBER.

Discussion

22.	The CISC stands for ___________(a) Computer Instruction Set Compliment(b) Complete Instruction Set Compliment(c) Computer Indexed Set Components(d) Complex Instruction set computerThis question was posed to me in semester exam.Asked question is from CISC and RISC Processors in chapter Arithmetic of Computer Architecture
Answer» Right choice is (d) Complex Instruction set computer Explanation: CISC is a computer ARCHITECTURE where in the processor performs more complex OPERATIONS in one STEP.

Discussion

23.	To increase the speed of memory access in pipelining, we make use of _______(a) Special memory locations(b) Special purpose registers(c) Cache(d) BuffersThe question was asked during an interview for a job.My enquiry is from Pipe-lining in portion Arithmetic of Computer Architecture
Answer» Correct CHOICE is (c) CACHE Explanation: By USING the cache we can reduce the SPEED of memory access by a factor of 10.

Discussion

24.	The sign followed by the string of digits is called as ______(a) Significant(b) Determinant(c) Mantissa(d) ExponentI had been asked this question at a job interview.I would like to ask this question from Representation of Floating Number topic in division Arithmetic of Computer Architecture
Answer» Correct choice is (C) MANTISSA The best explanation: The mantissa also consists of the decimal POINT.

Discussion

25.	We make use of ______ circuits to implement multiplication.(a) Flip flops(b) Combinatorial(c) Fast adders(d) None of the mentionedI have been asked this question in examination.This question is from Multiplication in chapter Arithmetic of Computer Architecture
Answer» CORRECT option is (C) Fast adders The EXPLANATION: The fast adders are used to add the multiplied NUMBERS.

Discussion

26.	In a normal adder circuit, the delay obtained in a generation of the output is _______(a) 2n + 2(b) 2n(c) n + 2(d) None of the mentionedThis question was addressed to me in an online interview.My doubt is from Fast Adders topic in chapter Arithmetic of Computer Architecture
Answer» RIGHT answer is (a) 2N + 2 The explanation: The 2n delay CAUSE of the carry generation and the 2 delay cause of the XOR OPERATION.

Discussion

27.	The step where in the results stored in the temporary register is transferred into the permanent register is called as ______(a) Final step(b) Commitment step(c) Last step(d) Inception stepThis question was addressed to me in an interview.I need to ask this question from Superscalar Processors in portion Arithmetic of Computer Architecture
Answer» The CORRECT OPTION is (b) Commitment step For EXPLANATION I would SAY: None.

Discussion

28.	If a unit completes its task before the allotted time period, then _______(a) It’ll perform some other task in the remaining time(b) Its time gets reallocated to a different task(c) It’ll remain idle for the remaining time(d) None of the mentionedThe question was posed to me in exam.I'm obligated to ask this question of Pipe-lining in section Arithmetic of Computer Architecture
Answer» CORRECT OPTION is (c) It’ll remain idle for the remaining time Explanation: NONE.

Discussion

29.	The Sun micro systems processors usually follow _____ architecture.(a) CISC(b) ISA(c) ULTRA SPARC(d) RISCThe question was asked by my school principal while I was bunking the class.I need to ask this question from CISC and RISC Processors topic in division Arithmetic of Computer Architecture
Answer» RIGHT answer is (d) RISC Explanation: The Risc MACHINE AIMS at reducing the INSTRUCTION set of the computer.

Discussion

30.	The bits 1 & 1 are recorded as _______ in bit-pair recording.(a) -1(b) 0(c) +1(d) both -1 and 0The question was posed to me in a job interview.I need to ask this question from Multiplication topic in chapter Arithmetic of Computer Architecture
Answer» The CORRECT choice is (d) both -1 and 0 To elaborate: Its ‘-1’when the PREVIOUS bit is 0 and ‘0’ when the previous bit is 1.

Discussion

31.	The iconic feature of the RISC machine among the following is _______(a) Reduced number of addressing modes(b) Increased memory size(c) Having a branch delay slot(d) All of the mentionedI got this question in an interview.This key question is from CISC and RISC Processors topic in division Arithmetic of Computer Architecture
Answer» The CORRECT answer is (C) Having a BRANCH delay SLOT The best explanation: A branch delay slot is an instruction space immediately following a jump or branch.

Discussion

32.	The periods of time when the unit is idle is called as _____(a) Stalls(b) Bubbles(c) Hazards(d) Both Stalls and BubblesI have been asked this question in an international level competition.The above asked question is from Pipe-lining topic in division Arithmetic of Computer Architecture
Answer» CORRECT choice is (d) Both Stalls and Bubbles The BEST I can EXPLAIN: The stalls are a type of HAZARDS that affect a pipelined SYSTEM.

Discussion

33.	The method used to reduce the maximum number of summands by half is _______(a) Fast multiplication(b) Bit-pair recording(c) Quick multiplication(d) None of the mentionedThe question was posed to me in my homework.Question is from Multiplication topic in portion Arithmetic of Computer Architecture
Answer» The correct option is (B) Bit-pair recording The BEST I can EXPLAIN: It reduces the NUMBER of summands by CONCATENATING them.

Discussion

34.	In pipelining the task which requires the least time is performed first.(a) True(b) FalseThis question was posed to me at a job interview.My question is taken from Pipe-lining topic in division Arithmetic of Computer Architecture
Answer» RIGHT option is (B) False To explain: This is DONE to AVOID starvation of the longer task.

Discussion

35.	The product of 1101 & 1011 is ______(a) 10001111(b) 10101010(c) 11110000(d) 11001100The question was posed to me in an internship interview.This interesting question is from Multiplication topic in portion Arithmetic of Computer Architecture
Answer» The CORRECT answer is (a) 10001111 Best EXPLANATION: The above operation is performed using BINARY MULTIPLICATION.

Discussion

36.	In full adders the sum circuit is implemented using ________(a) And & or gates(b) NAND gate(c) XOR(d) XNORI have been asked this question in a national level competition.Question is from Fast Adders topic in section Arithmetic of Computer Architecture
Answer» RIGHT ANSWER is (c) XOR Easy EXPLANATION: SUM = a ^ B ^ c (‘^’ indicates XOR operation).

Discussion

37.	______have been developed specifically for pipelined systems.(a) Utility software(b) Speed up utilities(c) Optimizing compilers(d) None of the mentionedI have been asked this question by my school teacher while I was bunking the class.The doubt is from Pipe-lining topic in section Arithmetic of Computer Architecture
Answer» CORRECT option is (c) Optimizing COMPILERS The explanation: The compilers which are designed to REMOVE redundant parts of the code are CALLED as optimizing compilers.

Discussion

38.	The multiplicand and the control signals are passed through to the n-bit adder via _____(a) MUX(b) DEMUX(c) Encoder(d) DecoderThis question was posed to me in semester exam.Enquiry is from Multiplication in portion Arithmetic of Computer Architecture
Answer» CORRECT choice is (a) MUX To EXPLAIN I would SAY: NONE.

Discussion

39.	A _______ gate is used to detect the occurrence of an overflow.(a) NAND(b) XOR(c) XNOR(d) ANDThe question was posed to me at a job interview.My question is taken from Fast Adders topic in portion Arithmetic of Computer Architecture
Answer» Correct option is (b) XOR To EXPLAIN: The overflow is detected by cn^cn-1 (‘^’ indicates XOR OPERATION).

Discussion

40.	A special unit used to govern the out of order execution of the instructions is called as ______(a) Commitment unit(b) Temporal unit(c) Monitor(d) Supervisory unitThis question was posed to me in a job interview.I would like to ask this question from Superscalar Processors in division Arithmetic of Computer Architecture
Answer» Correct answer is (a) Commitment unit Explanation: This unit MONITORS the EXECUTION of the instructions and makes sure that the FINAL RESULT is in order.

Discussion

41.	In 32 bit representation the scale factor as a range of ________(a) -128 to 127(b) -256 to 255(c) 0 to 255(d) None of the mentionedI got this question during an online interview.The question is from Representation of Floating Number in portion Arithmetic of Computer Architecture
Answer» The CORRECT ANSWER is (a) -128 to 127 The explanation: Since the exponent FIELD has only 8 bits to store the value.

Discussion

42.	Pipe-lining is a unique feature of _______(a) RISC(b) CISC(c) ISA(d) IANAI had been asked this question in an interview.The doubt is from CISC and RISC Processors topic in portion Arithmetic of Computer Architecture
Answer» The CORRECT CHOICE is (a) RISC The BEST explanation: The RISC machine architecture was the first to IMPLEMENT pipe-lining.

Discussion

43.	In CISC architecture most of the complex instructions are stored in _____(a) Register(b) Diodes(c) CMOS(d) TransistorsThis question was addressed to me in unit test.The origin of the question is CISC and RISC Processors topic in division Arithmetic of Computer Architecture
Answer» CORRECT option is (d) Transistors The explanation is: In CISC ARCHITECTURE more emphasis is GIVEN on the instruction set and the instructions take over a cycle to complete.

Discussion

44.	The computer architecture aimed at reducing the time of execution of instructions is ________(a) CISC(b) RISC(c) ISA(d) ANNAThe question was posed to me by my college director while I was bunking the class.This intriguing question comes from CISC and RISC Processors in section Arithmetic of Computer Architecture
Answer» The CORRECT answer is (b) RISC Easiest explanation: The RISC STANDS for REDUCED Instruction Set Computer.

Discussion

45.	The fetch and execution cycles are interleaved with the help of ________(a) Modification in processor architecture(b) Clock(c) Special unit(d) Control unitI have been asked this question in an interview for internship.The doubt is from Pipe-lining in division Arithmetic of Computer Architecture
Answer» Right option is (b) Clock For EXPLANATION I would say: The TIME cycle of the clock is adjusted to perform the interleaving.

Discussion

46.	In IEEE 32-bit representations, the mantissa of the fraction is said to occupy ______ bits.(a) 24(b) 23(c) 20(d) 16I had been asked this question in an interview for internship.This question is from Representation of Floating Number in portion Arithmetic of Computer Architecture
Answer» The correct choice is (b) 23 For EXPLANATION I WOULD say: The mantissa is made to occupy 23 BITS, with 8 bit EXPONENT.

Discussion

47.	Which option is true regarding the carry in the ripple adders?(a) Are generated at the beginning only(b) Must travel through the configuration(c) Is generated at the end of each operation(d) None of the mentionedThis question was posed to me in quiz.My question comes from Fast Adders in division Arithmetic of Computer Architecture
Answer» The correct choice is (b) Must TRAVEL through the configuration Best EXPLANATION: The carry must pass through the configuration of the CIRCUIT TILL it reaches the particular step.

Discussion

48.	Since it uses the out of order mode of execution, the results are stored in ______(a) Buffers(b) Special memory locations(c) Temporary registers(d) TLBI got this question in quiz.My question comes from Superscalar Processors topic in section Arithmetic of Computer Architecture
Answer» Right option is (c) TEMPORARY registers The BEST I can EXPLAIN: The RESULTS are stored in temporary locations and are arranged AFTERWARD.

Discussion

49.	The ______ plays a very vital role in case of super scalar processors.(a) Compilers(b) Motherboard(c) Memory(d) PeripheralsI got this question in an internship interview.This is a very interesting question from Superscalar Processors topic in section Arithmetic of Computer Architecture
Answer» The correct choice is (a) Compilers The EXPLANATION: The compilers are programmed to ARRANGE the instructions to GET more THROUGHPUT.

Discussion

50.	The logic operations are implemented using _______ circuits.(a) Bridge(b) Logical(c) Combinatorial(d) GateThis question was posed to me during an interview.The doubt is from Fast Adders in section Arithmetic of Computer Architecture
Answer» Correct ANSWER is (C) Combinatorial The best I can EXPLAIN: The combinatorial circuits means, USING the basic UNIVERSAL gates.

Discussion

Explore topic-wise InterviewSolutions in .

Out of the following which is not a CISC machine.(a) IBM 370/168(b) VAX 11/780(c) Intel 80486(d) Motorola A567The question was posed to me in an interview for internship.The query is from CISC and RISC Processors topic in chapter Arithmetic of Computer Architecture

In super-scalar processors, ________ mode of execution is used.(a) In-order(b) Post order(c) Out of order(d) None of the mentionedI had been asked this question in final exam.I'm obligated to ask this question of Superscalar Processors topic in section Arithmetic of Computer Architecture

The throughput of a super scalar processor is _______(a) less than 1(b) 1(c) More than 1(d) Not KnownThis question was posed to me by my school principal while I was bunking the class.My question is based upon Superscalar Processors in chapter Arithmetic of Computer Architecture

The logic operations are simpler to implement using logic circuits.(a) True(b) FalseI had been asked this question during an interview.My query is from Fast Adders topic in division Arithmetic of Computer Architecture

The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________(a) Half adders(b) Full adders(c) Ripple adders(d) Fast addersI have been asked this question in exam.My question is taken from Fast Adders topic in division Arithmetic of Computer Architecture

The pipelining process is also called as ______(a) Superscalar operation(b) Assembly line operation(c) Von Neumann cycle(d) None of the mentionedThe question was asked in my homework.Asked question is from Pipe-lining in chapter Arithmetic of Computer Architecture

The product of -13 & 11 is ______________(a) 1100110011(b) 1101110001(c) 1010101010(d) 1111111000I got this question in final exam.This interesting question is from Multiplication topic in portion Arithmetic of Computer Architecture

The multiplier is stored in ______(a) PC Register(b) Shift register(c) Cache(d) None of the mentionedI got this question during an interview.This is a very interesting question from Multiplication topic in portion Arithmetic of Computer Architecture

When the processor executes multiple instructions at a time it is said to use _______(a) single issue(b) Multiplicity(c) Visualization(d) Multiple issuesThe question was asked during an online exam.My query is from Superscalar Processors in chapter Arithmetic of Computer Architecture

In super-scalar mode, all the similar instructions are grouped and executed together.(a) True(b) FalseThis question was posed to me in quiz.My enquiry is from Superscalar Processors in portion Arithmetic of Computer Architecture

Both the CISC and RISC architectures have been developed to reduce the ______(a) Cost(b) Time delay(c) Semantic gap(d) All of the mentionedThis question was posed to me during an interview for a job.My question is from CISC and RISC Processors in section Arithmetic of Computer Architecture

________ constitute the representation of the floating number.(a) Sign(b) Significant digits(c) Scale factor(d) All of the mentionedThe question was posed to me in unit test.My question is based upon Representation of Floating Number topic in portion Arithmetic of Computer Architecture

The multiplier -6(11010) is recorded as _______(a) 0-1-2(b) 0-1+1-10(c) -2-10(d) None of the mentionedThe question was posed to me in unit test.The query is from Multiplication topic in chapter Arithmetic of Computer Architecture

The final addition sum of the numbers, 0110 & 0110 is ____________(a) 1101(b) 1111(c) 1001(d) 1010The question was asked in an online interview.This intriguing question comes from Fast Adders in chapter Arithmetic of Computer Architecture

The usual implementation of the carry circuit involves _________(a) And & or gates(b) XOR(c) NAND(d) XNORThe question was posed to me in an online interview.My question is taken from Fast Adders topic in division Arithmetic of Computer Architecture

Each stage in pipelining should be completed within ___________ cycle.(a) 1(b) 2(c) 3(d) 4This question was addressed to me in class test.Question is taken from Pipe-lining topic in division Arithmetic of Computer Architecture

To increase the speed of memory access in pipelining, we make use of _______(a) Special memory locations(b) Special purpose registers(c) Cache(d) BuffersThe question was asked during an interview for a job.My enquiry is from Pipe-lining in portion Arithmetic of Computer Architecture

The sign followed by the string of digits is called as ______(a) Significant(b) Determinant(c) Mantissa(d) ExponentI had been asked this question at a job interview.I would like to ask this question from Representation of Floating Number topic in division Arithmetic of Computer Architecture

We make use of ______ circuits to implement multiplication.(a) Flip flops(b) Combinatorial(c) Fast adders(d) None of the mentionedI have been asked this question in examination.This question is from Multiplication in chapter Arithmetic of Computer Architecture

In a normal adder circuit, the delay obtained in a generation of the output is _______(a) 2n + 2(b) 2n(c) n + 2(d) None of the mentionedThis question was addressed to me in an online interview.My doubt is from Fast Adders topic in chapter Arithmetic of Computer Architecture

The Sun micro systems processors usually follow _____ architecture.(a) CISC(b) ISA(c) ULTRA SPARC(d) RISCThe question was asked by my school principal while I was bunking the class.I need to ask this question from CISC and RISC Processors topic in division Arithmetic of Computer Architecture

The bits 1 & 1 are recorded as _______ in bit-pair recording.(a) -1(b) 0(c) +1(d) both -1 and 0The question was posed to me in a job interview.I need to ask this question from Multiplication topic in chapter Arithmetic of Computer Architecture

The periods of time when the unit is idle is called as _____(a) Stalls(b) Bubbles(c) Hazards(d) Both Stalls and BubblesI have been asked this question in an international level competition.The above asked question is from Pipe-lining topic in division Arithmetic of Computer Architecture

The method used to reduce the maximum number of summands by half is _______(a) Fast multiplication(b) Bit-pair recording(c) Quick multiplication(d) None of the mentionedThe question was posed to me in my homework.Question is from Multiplication topic in portion Arithmetic of Computer Architecture

In pipelining the task which requires the least time is performed first.(a) True(b) FalseThis question was posed to me at a job interview.My question is taken from Pipe-lining topic in division Arithmetic of Computer Architecture

The product of 1101 & 1011 is ______(a) 10001111(b) 10101010(c) 11110000(d) 11001100The question was posed to me in an internship interview.This interesting question is from Multiplication topic in portion Arithmetic of Computer Architecture

In full adders the sum circuit is implemented using ________(a) And & or gates(b) NAND gate(c) XOR(d) XNORI have been asked this question in a national level competition.Question is from Fast Adders topic in section Arithmetic of Computer Architecture

The multiplicand and the control signals are passed through to the n-bit adder via _____(a) MUX(b) DEMUX(c) Encoder(d) DecoderThis question was posed to me in semester exam.Enquiry is from Multiplication in portion Arithmetic of Computer Architecture

A _______ gate is used to detect the occurrence of an overflow.(a) NAND(b) XOR(c) XNOR(d) ANDThe question was posed to me at a job interview.My question is taken from Fast Adders topic in portion Arithmetic of Computer Architecture

In 32 bit representation the scale factor as a range of ________(a) -128 to 127(b) -256 to 255(c) 0 to 255(d) None of the mentionedI got this question during an online interview.The question is from Representation of Floating Number in portion Arithmetic of Computer Architecture

Pipe-lining is a unique feature of _______(a) RISC(b) CISC(c) ISA(d) IANAI had been asked this question in an interview.The doubt is from CISC and RISC Processors topic in portion Arithmetic of Computer Architecture

In CISC architecture most of the complex instructions are stored in _____(a) Register(b) Diodes(c) CMOS(d) TransistorsThis question was addressed to me in unit test.The origin of the question is CISC and RISC Processors topic in division Arithmetic of Computer Architecture

The fetch and execution cycles are interleaved with the help of ________(a) Modification in processor architecture(b) Clock(c) Special unit(d) Control unitI have been asked this question in an interview for internship.The doubt is from Pipe-lining in division Arithmetic of Computer Architecture

In IEEE 32-bit representations, the mantissa of the fraction is said to occupy ______ bits.(a) 24(b) 23(c) 20(d) 16I had been asked this question in an interview for internship.This question is from Representation of Floating Number in portion Arithmetic of Computer Architecture

Since it uses the out of order mode of execution, the results are stored in ______(a) Buffers(b) Special memory locations(c) Temporary registers(d) TLBI got this question in quiz.My question comes from Superscalar Processors topic in section Arithmetic of Computer Architecture

The ______ plays a very vital role in case of super scalar processors.(a) Compilers(b) Motherboard(c) Memory(d) PeripheralsI got this question in an internship interview.This is a very interesting question from Superscalar Processors topic in section Arithmetic of Computer Architecture

The logic operations are implemented using _______ circuits.(a) Bridge(b) Logical(c) Combinatorial(d) GateThis question was posed to me during an interview.The doubt is from Fast Adders in section Arithmetic of Computer Architecture