In a normal adder circuit, the delay obtained in a generation of the output is _______(a) 2n + 2(b) 2n(c) n + 2(d) None of the mentionedThis question was addressed to me in an online interview.My doubt is from Fast Adders topic in chapter Arithmetic of Computer Architecture

In a normal adder circuit, the delay obtained in a generation of the o

1.	In a normal adder circuit, the delay obtained in a generation of the output is _______(a) 2n + 2(b) 2n(c) n + 2(d) None of the mentionedThis question was addressed to me in an online interview.My doubt is from Fast Adders topic in chapter Arithmetic of Computer Architecture
Answer» RIGHT answer is (a) 2N + 2 The explanation: The 2n delay CAUSE of the carry generation and the 2 delay cause of the XOR OPERATION.

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In a normal adder circuit, the delay obtained in a generation of the output is _______(a) 2n + 2(b) 2n(c) n + 2(d) None of the mentionedThis question was addressed to me in an online interview.My doubt is from Fast Adders topic in chapter Arithmetic of Computer Architecture

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