191 + Interview Questions in Memory System in Computer Architecture Page 1 InterviewSolution

1.	The key factor/s in commercial success of a computer is/are ________(a) Performance(b) Cost(c) Speed(d) Both Performance and CostThis question was addressed to me in semester exam.Asked question is from Performance of Caches in chapter Memory System of Computer Architecture
Answer» CORRECT OPTION is (d) Both PERFORMANCE and Cost Explanation: The performance and cost of the computer SYSTEM is a key DECIDER in the commercial success of the system.

Discussion

2.	What does the end instruction do?(a) It ends the generation of a signal(b) It ends the complete generation process(c) It starts a new instruction fetch cycle and resets the counter(d) It is used to shift the control to the processorI got this question in semester exam.My question is from Hardwired Control in portion Memory System of Computer Architecture
Answer» Right answer is (c) It starts a NEW INSTRUCTION fetch CYCLE and resets the counter To elaborate: It is BASICALLY used to start the GENERATION of a new signal.

Discussion

3.	What does the hardwired control generator consist of?(a) Decoder/encoder(b) Condition codes(c) Control step counter(d) All of the mentionedI got this question in examination.This interesting question is from Hardwired Control in section Memory System of Computer Architecture
Answer» The correct CHOICE is (d) All of the mentioned The EXPLANATION is: The CU uses the above BLOCKS and IR to PRODUCE the NECESSARY signal.

Discussion

4.	The general purpose registers are combined into a block called as ______(a) Register bank(b) Register Case(c) Register file(d) None of the mentionedI got this question in an online quiz.The query is from Multiple BUS Organistaion in chapter Memory System of Computer Architecture
Answer» CORRECT choice is (c) Register file The best I can EXPLAIN: To make the access of the registers EASIER, we CLASSIFY them into register FILES.

Discussion

5.	There exists a separate block consisting of various units to decode an instruction.(a) True(b) FalseThe question was asked in unit test.Asked question is from Multiple BUS Organistaion topic in section Memory System of Computer Architecture
Answer» Correct option is (a) True Best EXPLANATION: This BLOCK is used to DECODE the instruction and PLACE it in the IR.

Discussion

6.	ANSI stands for _____________(a) American National Standards Institute(b) American National Standard Interface(c) American Network Standard Interfacing(d) American Network Security InterruptThis question was posed to me during an interview.This intriguing question comes from Single BUS Organisation in chapter Memory System of Computer Architecture
Answer» The CORRECT CHOICE is (a) AMERICAN National Standards Institute Explanation: It is one of the standards of DEVELOPING a BUS.

Discussion

7.	_________ signal enables the processor to wait for the memory operation to complete.(a) MFC(b) TLB(c) WMFC(d) ALBI have been asked this question during an online interview.This question is from Single BUS Organisation in portion Memory System of Computer Architecture
Answer» CORRECT ANSWER is (c) WMFC For EXPLANATION: This signal stands for WAIT For MEMORY Function Complete.

Discussion

8.	When two or more clock cycles are used to complete data transfer it is called as ________(a) Single phase clocking(b) Multi-phase clocking(c) Edge triggered clocking(d) None of the mentionedThe question was posed to me by my school teacher while I was bunking the class.I would like to ask this question from Single BUS Organisation in division Memory System of Computer Architecture
Answer» CORRECT choice is (B) Multi-phase clocking Explanation: This is BASICALLY used in SYSTEMS without edge-triggered flip flops.

Discussion

9.	The registers, ALU and the interconnecting path together are called as ______(a) Control path(b) Flow path(c) Data path(d) None of the mentionedThe question was asked in unit test.The doubt is from Single BUS Organisation topic in division Memory System of Computer Architecture
Answer» CORRECT answer is (C) Data path Easy EXPLANATION: None.

Discussion

10.	The method of placing the heads and the discs in an air tight environment is also called as ______(a) RAID Arrays(b) ATP tech(c) Winchester technology(d) Fleming reductionI had been asked this question during an online exam.Question is taken from Secondary Storage topic in portion Memory System of Computer Architecture
Answer» Right option is (c) WINCHESTER technology The EXPLANATION is: The DISKS and the heads operate FASTER due to the absence of the dust particles.

Discussion

11.	The program is divided into operable parts called as _________(a) Frames(b) Segments(c) Pages(d) SheetsThe question was posed to me in an internship interview.Enquiry is from Virtual Memory topic in division Memory System of Computer Architecture
Answer» The CORRECT answer is (b) Segments To ELABORATE: The program is divided into PARTS called as segments for ease of EXECUTION.

Discussion

12.	The physical memory is not as large as the address space spanned by the processor.(a) True(b) FalseI have been asked this question in quiz.My doubt is from Virtual Memory in portion Memory System of Computer Architecture
Answer» Right CHOICE is (a) True The best explanation: This is ONE of the MAIN REASONS for the usage of virtual MEMORIES.

Discussion

13.	The performance depends on ________(a) The speed of execution only(b) The speed of fetch and execution(c) The speed of fetch only(d) The hardware of the system onlyThis question was posed to me during an interview.My doubt is from Performance of Caches in section Memory System of Computer Architecture
Answer» Correct option is (B) The speed of fetch and execution To EXPLAIN I would say: The performance of a SYSTEM is decided by how quick an instruction is brought into the system and executed.

Discussion

14.	A common measure of performance is ________(a) Price/performance ratio(b) Performance/price ratio(c) Operation/price ratio(d) None of the mentionedI got this question in an international level competition.I'm obligated to ask this question of Performance of Caches in portion Memory System of Computer Architecture
Answer» Right OPTION is (a) Price/performance ratio Easiest EXPLANATION: If this measure is LESS than one then the SYSTEM is OPTIMAL.

Discussion

15.	The benefit of using this approach is ________(a) It is cost effective(b) It is highly efficient(c) It is very reliable(d) It increases the speed of operationThe question was posed to me by my school principal while I was bunking the class.The doubt is from Hardwired Control in portion Memory System of Computer Architecture
Answer» CORRECT ANSWER is (d) It INCREASES the SPEED of operation Explanation: NONE.

Discussion

16.	________ are the different type/s of generating control signals.(a) Micro-programmed(b) Hardwired(c) Micro-instruction(d) Both Micro-programmed and HardwiredI have been asked this question in final exam.The above asked question is from Hardwired Control topic in section Memory System of Computer Architecture
Answer» Right choice is (d) Both Micro-programmed and Hardwired Explanation: The above is used to GENERATE control SIGNALS in DIFFERENT types of SYSTEM ARCHITECTURES.

Discussion

17.	In ______ technology, the implementation of the register file is by using an array of memory locations.(a) VLSI(b) ANSI(c) ISA(d) ASCII got this question during an online exam.The above asked question is from Multiple BUS Organistaion topic in division Memory System of Computer Architecture
Answer» CORRECT choice is (a) VLSI The EXPLANATION is: By doing so the access of the REGISTERS can be made FASTER.

Discussion

18.	The input and output of the registers are governed by __________(a) Transistors(b) Diodes(c) Gates(d) SwitchesThe question was posed to me during an online interview.Asked question is from Single BUS Organisation in division Memory System of Computer Architecture
Answer» The CORRECT CHOICE is (d) Switches The BEST I can EXPLAIN: NONE.

Discussion

19.	The set of corresponding tracks on all surfaces of a stack of disks form a ______(a) Cluster(b) Cylinder(c) Group(d) SetI have been asked this question during an internship interview.The origin of the question is Secondary Storage in portion Memory System of Computer Architecture
Answer» RIGHT OPTION is (b) Cylinder To explain: The DATA is stored in these sections CALLED as CYLINDERS.

Discussion

20.	If hit rates are well below 0.9, then they’re called as speedy computers.(a) True(b) FalseThe question was asked by my school principal while I was bunking the class.This interesting question is from Cache Miss and Hit topic in portion Memory System of Computer Architecture
Answer» Correct OPTION is (B) False The explanation: It has to be above 0.9 for speedy COMPUTERS.

Discussion

21.	The binary address issued to data or instructions are called as ______(a) Physical address(b) Location(c) Relocatable address(d) Logical addressThis question was addressed to me in an online quiz.My enquiry is from Virtual Memory topic in portion Memory System of Computer Architecture
Answer» RIGHT choice is (d) Logical ADDRESS For EXPLANATION I WOULD say: The logical address is the random address GENERATED by the processor.

Discussion

22.	______ translates the logical address into a physical address.(a) MMU(b) Translator(c) Compiler(d) LinkerI have been asked this question in a job interview.This key question is from Virtual Memory topic in section Memory System of Computer Architecture
Answer» Correct CHOICE is (a) MMU Explanation: The MMU TRANSLATES the logical address into a physical address by ADDING an offset.

Discussion

23.	The air pressure can be countered by putting ______ in the head-disc surface arrangement.(a) Air filter(b) Spring mechanism(c) coolant(d) None of the mentionedI have been asked this question in an interview for internship.I'd like to ask this question from Secondary Storage topic in chapter Memory System of Computer Architecture
Answer» Right CHOICE is (b) Spring mechanism The explanation is: The spring mechanism pushes the HEAD along the SURFACE to reduce the air PRESSURE EFFECT.

Discussion

24.	The read/write heads must be near to disk surfaces for better storage.(a) True(b) FalseThis question was addressed to me in homework.My question is taken from Secondary Storage topic in portion Memory System of Computer Architecture
Answer» The correct answer is (a) True The best I can EXPLAIN: By maintaining the heads near to the surface GREATER bit DENSITIES can be achieved.

Discussion

25.	The virtual memory basically stores the next segment of data to be executed on the _________(a) Secondary storage(b) Disks(c) RAM(d) ROMThe question was asked in quiz.This key question is from Virtual Memory in division Memory System of Computer Architecture
Answer» The CORRECT ANSWER is (a) SECONDARY storage Explanation: NONE.

Discussion

26.	The LRU provides very bad performance when it comes to _________(a) Blocks being accessed is sequential(b) When the blocks are randomised(c) When the consecutive blocks accessed are in the extremes(d) None of the mentionedI got this question by my college director while I was bunking the class.Asked question is from Replacement Algorithms topic in chapter Memory System of Computer Architecture
Answer» Correct OPTION is (a) BLOCKS being accessed is sequential The explanation is: The LRU in CASE of the sequential blocks as to waste its one cycle just INCREMENTING the counters.

Discussion

27.	The memory transfers between two variable speed devices are always done at the speed of the faster device.(a) True(b) FalseThe question was posed to me in an international level competition.I'm obligated to ask this question of Performance of Caches in chapter Memory System of Computer Architecture
Answer» The CORRECT option is (a) True For explanation I WOULD say: NONE.

Discussion

28.	The bit used to indicate whether the block was recently used or not is _______(a) Idol bit(b) Control bit(c) Reference bit(d) Dirty bitThis question was posed to me at a job interview.I'd like to ask this question from Mapping Functions topic in chapter Memory System of Computer Architecture
Answer» RIGHT answer is (d) Dirty bit The explanation: The dirty bit is used to SHOW that the block was RECENTLY modified and for a REPLACEMENT ALGORITHM.

Discussion

29.	The data can be accessed from the disk using _________(a) Surface number(b) Sector number(c) Track number(d) All of the mentionedThe question was posed to me during an internship interview.My question comes from Secondary Storage topic in division Memory System of Computer Architecture
Answer» CORRECT OPTION is (d) All of the mentioned For EXPLANATION: NONE.

Discussion

30.	The disk drive is connected to the system by using the _____(a) PCI bus(b) SCSI bus(c) HDMI(d) ISAI got this question in class test.My question comes from Secondary Storage topic in chapter Memory System of Computer Architecture
Answer» The correct OPTION is (B) SCSI bus For explanation I WOULD SAY: None.

Discussion

31.	The algorithm which replaces the block which has not been referenced for a while is called _____(a) LRU(b) ORF(c) Direct(d) Both LRU and ORFI have been asked this question in unit test.This question is from Replacement Algorithms topic in division Memory System of Computer Architecture
Answer» Correct ANSWER is (a) LRU Explanation: LRU stands for LEAST RECENTLY USED first.

Discussion

32.	CISC stands for _________(a) Complete Instruction Sequential Compilation(b) Computer Integrated Sequential Compiler(c) Complex Instruction Set Computer(d) Complex Instruction Sequential CompilationI have been asked this question during an interview.I want to ask this question from Multiple BUS Organistaion in section Memory System of Computer Architecture
Answer» The correct OPTION is (c) COMPLEX INSTRUCTION Set Computer Easiest explanation: The CISC machines are well adept at HANDLING MULTIPLE BUS organisation.

Discussion

33.	The main advantage of multiple bus organisation over a single bus is __________(a) Reduction in the number of cycles for execution(b) Increase in size of the registers(c) Better Connectivity(d) None of the mentionedI have been asked this question during an internship interview.My enquiry is from Multiple BUS Organistaion in portion Memory System of Computer Architecture
Answer» The correct OPTION is (a) Reduction in the NUMBER of cycles for execution Easiest EXPLANATION: NONE.

Discussion

34.	In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when _____ occurs.(a) Delay(b) Miss(c) Hit(d) Delayed hitI had been asked this question in an online quiz.Question is from Cache Miss and Hit topic in portion Memory System of Computer Architecture
Answer» CORRECT option is (b) Miss For EXPLANATION: Miss usually occurs when the memory BLOCK required is not PRESENT in the cache.

Discussion

35.	A control bit called _________ has to be provided to each block in set-associative.(a) Idol bit(b) Valid bit(c) Reference bit(d) All of the mentionedThe question was asked in unit test.I would like to ask this question from Mapping Functions in portion Memory System of Computer Architecture
Answer» Correct choice is (b) Valid bit For EXPLANATION I WOULD SAY: The valid bit is used to indicate that the block HOLDS valid INFORMATION.

Discussion

36.	When consecutive memory locations are accessed only one module is accessed at a time.(a) True(b) FalseI have been asked this question during an online exam.This interesting question is from Cache Miss and Hit topic in division Memory System of Computer Architecture
Answer» Correct OPTION is (a) True To explain I would say: In a MODULAR approach to memory structuring only ONE module can be accessed at a time.

Discussion

37.	In set-associative technique, the blocks are grouped into ______ sets.(a) 4(b) 8(c) 12(d) 6I had been asked this question in an interview.Asked question is from Mapping Functions in section Memory System of Computer Architecture
Answer» Correct answer is (d) 6 The EXPLANATION is: The set-associative TECHNIQUE GROUPS the BLOCKS into different sets.

Discussion

38.	Which register is connected to the MUX?(a) Y(b) Z(c) R0(d) TempI have been asked this question in a national level competition.Query is from Single BUS Organisation in portion Memory System of Computer Architecture
Answer» Correct choice is (a) Y The explanation is: The MUX can EITHER read the operand from the Y register or INCREMENT the PC.

Discussion

39.	The drawback of Manchester encoding is _________(a) The cost of the encoding scheme(b) The speed of encoding the data(c) The Latency offered(d) The low bit storage density providedThis question was addressed to me in homework.My doubt is from Secondary Storage in portion Memory System of Computer Architecture
Answer» Correct OPTION is (d) The low bit storage density provided The BEST explanation: The space required to represent each bit must be large enough to accommodate two CHANGES in magnetization.

Discussion

40.	__________ is used to implement virtual memory organisation.(a) Page table(b) Frame table(c) MMU(d) None of the mentionedI had been asked this question in an online quiz.The above asked question is from Virtual Memory in portion Memory System of Computer Architecture
Answer» The correct ANSWER is (C) MMU The EXPLANATION: The MMU STANDS for Memory Management Unit.

Discussion

41.	The case/s where micro-programmed can perform well _______________(a) When it requires to check the condition codes(b) When it has to choose between the two alternatives(c) When it is triggered by an interrupt(d) None of the mentionedThe question was asked during a job interview.This key question is from Microprogrammed Control topic in section Memory System of Computer Architecture
Answer» RIGHT CHOICE is (d) NONE of the mentioned Explanation: None.

Discussion

42.	A word whose individual bits represent a control signal is ______(a) Command word(b) Control word(c) Co-ordination word(d) Generation wordThis question was posed to me in an online interview.Origin of the question is Microprogrammed Control topic in division Memory System of Computer Architecture
Answer» Correct OPTION is (b) Control word To explain I would SAY: The control word is used to get the different TYPES of control signals required.

Discussion

43.	The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4.BR…(a) True(b) FalseThis question was posed to me during a job interview.This key question is from Hardwired Control in section Memory System of Computer Architecture
Answer» The CORRECT ANSWER is (a) True To explain: The SIGNAL is generated USING the logic of the FORMULA above.

Discussion

44.	Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster.(a) A(b) B(c) Both take the same time(d) Insufficient informationI had been asked this question in my homework.This question is from Performance of Caches topic in section Memory System of Computer Architecture
Answer» CORRECT option is (a) A To explain I would say: NONE.

Discussion

45.	_______ is used to deal with the difference in the transfer rates between the drive and the bus.(a) Data repeaters(b) Enhancers(c) Data buffers(d) None of the mentionedI had been asked this question during an online exam.My doubt is from Secondary Storage topic in chapter Memory System of Computer Architecture
Answer» The CORRECT OPTION is (c) Data buffers Explanation: The buffers are ADDED to store the data from the fast device and to send it to the SLOWER device at its RATE.

Discussion

46.	To read the control words sequentially _________ is used.(a) PC(b) IR(c) UPC(d) None of the mentionedI have been asked this question in an internship interview.The question is from Microprogrammed Control topic in division Memory System of Computer Architecture
Answer» Right choice is (c) UPC Best explanation: The UPC STANDS for MICRO PROGRAM counter.

Discussion

47.	The main purpose of having memory hierarchy is to ________(a) Reduce access time(b) Provide large capacity(c) Reduce propagation time(d) Reduce access time & Provide large capacityI have been asked this question in an interview for internship.The doubt is from Performance of Caches topic in division Memory System of Computer Architecture
Answer» Right answer is (d) REDUCE access TIME & PROVIDE large capacity To explain: By using the memory HIERARCHY, we can increase the performance of the system.

Discussion

48.	The main objective of the computer system is ________(a) To provide optimal power operation(b) To provide the best performance at low cost(c) To provide speedy operation at low power consumption(d) All of the mentionedThis question was addressed to me in an interview.My question is taken from Performance of Caches topic in portion Memory System of Computer Architecture
Answer» Correct option is (b) To PROVIDE the best performance at low cost The best I can explain: An OPTIMAL SYSTEM provides the best performance at low COSTS.

Discussion

49.	Individual control words of the micro routine are called as ______(a) Micro task(b) Micro operation(c) Micro instruction(d) Micro commandI had been asked this question at a job interview.This is a very interesting question from Microprogrammed Control topic in chapter Memory System of Computer Architecture
Answer» CORRECT choice is (C) Micro instruction Best explanation: The each instruction which put TOGETHER PERFORMS the task.

Discussion

50.	In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU.(a) MUX(b) DE-MUX(c) En-CDS(d) None of the mentionedI got this question in class test.The above asked question is from Multiple BUS Organistaion in division Memory System of Computer Architecture
Answer» Correct answer is (a) MUX Best EXPLANATION: The MUX can be used to EITHER select the BUS or to INCREMENT the PC.

Discussion

Explore topic-wise InterviewSolutions in .

The key factor/s in commercial success of a computer is/are ________(a) Performance(b) Cost(c) Speed(d) Both Performance and CostThis question was addressed to me in semester exam.Asked question is from Performance of Caches in chapter Memory System of Computer Architecture

What does the hardwired control generator consist of?(a) Decoder/encoder(b) Condition codes(c) Control step counter(d) All of the mentionedI got this question in examination.This interesting question is from Hardwired Control in section Memory System of Computer Architecture

The general purpose registers are combined into a block called as ______(a) Register bank(b) Register Case(c) Register file(d) None of the mentionedI got this question in an online quiz.The query is from Multiple BUS Organistaion in chapter Memory System of Computer Architecture

There exists a separate block consisting of various units to decode an instruction.(a) True(b) FalseThe question was asked in unit test.Asked question is from Multiple BUS Organistaion topic in section Memory System of Computer Architecture

_________ signal enables the processor to wait for the memory operation to complete.(a) MFC(b) TLB(c) WMFC(d) ALBI have been asked this question during an online interview.This question is from Single BUS Organisation in portion Memory System of Computer Architecture

The registers, ALU and the interconnecting path together are called as ______(a) Control path(b) Flow path(c) Data path(d) None of the mentionedThe question was asked in unit test.The doubt is from Single BUS Organisation topic in division Memory System of Computer Architecture

The program is divided into operable parts called as _________(a) Frames(b) Segments(c) Pages(d) SheetsThe question was posed to me in an internship interview.Enquiry is from Virtual Memory topic in division Memory System of Computer Architecture

The physical memory is not as large as the address space spanned by the processor.(a) True(b) FalseI have been asked this question in quiz.My doubt is from Virtual Memory in portion Memory System of Computer Architecture

In ______ technology, the implementation of the register file is by using an array of memory locations.(a) VLSI(b) ANSI(c) ISA(d) ASCII got this question during an online exam.The above asked question is from Multiple BUS Organistaion topic in division Memory System of Computer Architecture

The input and output of the registers are governed by __________(a) Transistors(b) Diodes(c) Gates(d) SwitchesThe question was posed to me during an online interview.Asked question is from Single BUS Organisation in division Memory System of Computer Architecture

The set of corresponding tracks on all surfaces of a stack of disks form a ______(a) Cluster(b) Cylinder(c) Group(d) SetI have been asked this question during an internship interview.The origin of the question is Secondary Storage in portion Memory System of Computer Architecture

If hit rates are well below 0.9, then they’re called as speedy computers.(a) True(b) FalseThe question was asked by my school principal while I was bunking the class.This interesting question is from Cache Miss and Hit topic in portion Memory System of Computer Architecture

The binary address issued to data or instructions are called as ______(a) Physical address(b) Location(c) Relocatable address(d) Logical addressThis question was addressed to me in an online quiz.My enquiry is from Virtual Memory topic in portion Memory System of Computer Architecture

______ translates the logical address into a physical address.(a) MMU(b) Translator(c) Compiler(d) LinkerI have been asked this question in a job interview.This key question is from Virtual Memory topic in section Memory System of Computer Architecture

The read/write heads must be near to disk surfaces for better storage.(a) True(b) FalseThis question was addressed to me in homework.My question is taken from Secondary Storage topic in portion Memory System of Computer Architecture

The virtual memory basically stores the next segment of data to be executed on the _________(a) Secondary storage(b) Disks(c) RAM(d) ROMThe question was asked in quiz.This key question is from Virtual Memory in division Memory System of Computer Architecture

The memory transfers between two variable speed devices are always done at the speed of the faster device.(a) True(b) FalseThe question was posed to me in an international level competition.I'm obligated to ask this question of Performance of Caches in chapter Memory System of Computer Architecture

The bit used to indicate whether the block was recently used or not is _______(a) Idol bit(b) Control bit(c) Reference bit(d) Dirty bitThis question was posed to me at a job interview.I'd like to ask this question from Mapping Functions topic in chapter Memory System of Computer Architecture

The data can be accessed from the disk using _________(a) Surface number(b) Sector number(c) Track number(d) All of the mentionedThe question was posed to me during an internship interview.My question comes from Secondary Storage topic in division Memory System of Computer Architecture

The disk drive is connected to the system by using the _____(a) PCI bus(b) SCSI bus(c) HDMI(d) ISAI got this question in class test.My question comes from Secondary Storage topic in chapter Memory System of Computer Architecture

The algorithm which replaces the block which has not been referenced for a while is called _____(a) LRU(b) ORF(c) Direct(d) Both LRU and ORFI have been asked this question in unit test.This question is from Replacement Algorithms topic in division Memory System of Computer Architecture

A control bit called _________ has to be provided to each block in set-associative.(a) Idol bit(b) Valid bit(c) Reference bit(d) All of the mentionedThe question was asked in unit test.I would like to ask this question from Mapping Functions in portion Memory System of Computer Architecture

When consecutive memory locations are accessed only one module is accessed at a time.(a) True(b) FalseI have been asked this question during an online exam.This interesting question is from Cache Miss and Hit topic in division Memory System of Computer Architecture

In set-associative technique, the blocks are grouped into ______ sets.(a) 4(b) 8(c) 12(d) 6I had been asked this question in an interview.Asked question is from Mapping Functions in section Memory System of Computer Architecture

Which register is connected to the MUX?(a) Y(b) Z(c) R0(d) TempI have been asked this question in a national level competition.Query is from Single BUS Organisation in portion Memory System of Computer Architecture

__________ is used to implement virtual memory organisation.(a) Page table(b) Frame table(c) MMU(d) None of the mentionedI had been asked this question in an online quiz.The above asked question is from Virtual Memory in portion Memory System of Computer Architecture

A word whose individual bits represent a control signal is ______(a) Command word(b) Control word(c) Co-ordination word(d) Generation wordThis question was posed to me in an online interview.Origin of the question is Microprogrammed Control topic in division Memory System of Computer Architecture

The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4.BR…(a) True(b) FalseThis question was posed to me during a job interview.This key question is from Hardwired Control in section Memory System of Computer Architecture

To read the control words sequentially _________ is used.(a) PC(b) IR(c) UPC(d) None of the mentionedI have been asked this question in an internship interview.The question is from Microprogrammed Control topic in division Memory System of Computer Architecture

In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU.(a) MUX(b) DE-MUX(c) En-CDS(d) None of the mentionedI got this question in class test.The above asked question is from Multiple BUS Organistaion in division Memory System of Computer Architecture