191 + Interview Questions in Memory System in Computer Architecture Page 3 InterviewSolution

101.	The mode register is used to _______(a) Select the row or column data transfer mode(b) Select the mode of operation(c) Select mode of storing the data(d) All of the mentionedThe question was posed to me in unit test.The query is from Synchronous DRAM in section Memory System of Computer Architecture
Answer» Right ANSWER is (B) Select the mode of OPERATION The BEST I can explain: The mode register is USED to choose between burst mode or bit mode of operation.

Discussion

102.	The RAS and CAS signals are provided by the ______(a) Mode register(b) CS(c) Memory controller(d) None of the mentionedThe question was posed to me in final exam.Question is from Large Memories topic in division Memory System of Computer Architecture
Answer» Correct ANSWER is (C) MEMORY controller Easy explanation: The MULTIPLEXED signal of the controller is split into RAS and CAS.

Discussion

103.	The higher order bits of the address are used to _____(a) Specify the row address(b) Specify the column address(c) Input the CS(d) None of the mentionedThe question was asked in semester exam.I'd like to ask this question from Large Memories topic in section Memory System of Computer Architecture
Answer» RIGHT CHOICE is (a) Specify the row address The EXPLANATION: NONE.

Discussion

104.	The controller multiplexes the addresses after getting the _____ signal.(a) INTR(b) ACK(c) RESET(d) RequestI got this question in homework.I need to ask this question from Large Memories in division Memory System of Computer Architecture
Answer» The correct option is (d) REQUEST Best explanation: The controller gets the request from the DEVICE needing the memory read or write operation and then it MULTIPLEXES the address.

Discussion

105.	The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______(a) Memory sticks(b) Blue-ray devices(c) Flash memory(d) CMOSThis question was posed to me in an online interview.My query is from Read-Only Memory in portion Memory System of Computer Architecture
Answer» RIGHT answer is (c) Flash MEMORY To elaborate: The flash memory functions similar to the EEPROM but is MUCH CHEAPER.

Discussion

106.	The difference between DRAM’s and SDRAM’s is/are ________(a) The DRAM’s will not use the master slave relationship in data transfer(b) The SDRAM’s make use of clock(c) The SDRAM’s are more power efficient(d) None of the mentionedI got this question in an interview.Enquiry is from Synchronous DRAM topic in portion Memory System of Computer Architecture
Answer» The correct answer is (d) NONE of the mentioned To explain: The SDRAM’s MAKE use of CLOCK signals to synchronize their OPERATION.

Discussion

107.	The logical addresses generated by the cpu are mapped onto physical memory by ____________(a) Relocation register(b) TLB(c) MMU(d) None of the mentionedThe question was asked in an interview for internship.The question is from Static Memories in portion Memory System of Computer Architecture
Answer» Correct option is (C) MMU Easiest EXPLANATION: The MMU stands for memory management unit, which is used to map LOGICAL address onto the PHYSICAL address.

Discussion

108.	The capacitors lose the charge over time due to ________(a) The leakage resistance of the capacitor(b) The small current in the transistor after being turned on(c) The defect of the capacitor(d) None of the mentionedThe question was asked in an interview for job.The origin of the question is Asynchronous DRAM in chapter Memory System of Computer Architecture
Answer» The CORRECT choice is (a) The leakage RESISTANCE of the capacitor For explanation: The capacitor LOSES charge DUE to the backward current of the transistor and due to the small resistance.

Discussion

109.	The ROM chips are mainly used to store _______(a) System files(b) Root directories(c) Boot files(d) Driver filesI had been asked this question in unit test.This intriguing question comes from Read-Only Memory topic in division Memory System of Computer Architecture
Answer» The correct CHOICE is (c) BOOT FILES Explanation: The ROM chips are used to store boot files required for the system STARTUP.

Discussion

110.	The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______(a) Level 1 cache(b) Level 2 cache(c) Registers(d) TLBThis question was posed to me in an international level competition.Question is from Hierarchy of Memory topic in chapter Memory System of Computer Architecture
Answer» Correct ANSWER is (a) Level 1 cache Easy EXPLANATION: These MEMORY devices are generally used to map onto the data stored in the LARGER memories.

Discussion

111.	The drawback of building a large memory with DRAM is ______________(a) The large cost factor(b) The inefficient memory organisation(c) The Slow speed of operation(d) All of the mentionedThe question was asked by my college professor while I was bunking the class.This intriguing question comes from Hierarchy of Memory topic in portion Memory System of Computer Architecture
Answer» Correct answer is (c) The SLOW speed of operation To EXPLAIN: The DRAM’s were used for large memory MODULES for a LONG time until a substitute was found.

Discussion

112.	If the transistor gate is closed, then the ROM stores a value of 1.(a) True(b) FalseI had been asked this question in a job interview.My question is taken from Read-Only Memory topic in section Memory System of Computer Architecture
Answer» Correct answer is (B) False For explanation I would SAY: If the gate of the transistor is CLOSED then, the VALUE of zero is stored in the ROM.

Discussion

113.	To organise large memory chips we make use of ______(a) Integrated chips(b) Upgraded hardware(c) Memory modules(d) None of the mentionedThis question was addressed to me in class test.The query is from Large Memories topic in division Memory System of Computer Architecture
Answer» The correct CHOICE is (c) MEMORY modules Easiest explanation: The cell BLOCKS are ARRANGED and put in a memory module.

Discussion

114.	In SDRAM’s buffers are used to store data that is read or written.(a) True(b) FalseI have been asked this question in semester exam.My doubt stems from Synchronous DRAM topic in section Memory System of Computer Architecture
Answer» Correct choice is (a) True Easiest explanation: In SDRAM’s all the BYTES of data to be read or written are stored in the buffer until the operation is COMPLETE.

Discussion

115.	DDR SDRAM’s perform faster data transfer by _______(a) Integrating the hardware(b) Transferring on both edges(c) Improving the clock speeds(d) Increasing the bandwidthI had been asked this question in homework.This interesting question is from Synchronous DRAM in division Memory System of Computer Architecture
Answer» CORRECT option is (B) Transferring on both edges The EXPLANATION is: By transferring data on both the edges the bandwidth is effectively DOUBLED.

Discussion

116.	The disadvantage of the EEPROM is/are ________(a) The requirement of different voltages to read, write and store information(b) The Latency read operation(c) The inefficient memory mapping schemes used(d) All of the mentionedThe question was asked in examination.I'd like to ask this question from Read-Only Memory topic in division Memory System of Computer Architecture
Answer» Correct answer is (a) The requirement of different voltages to read, WRITE and STORE information Easiest explanation: NONE.

Discussion

117.	The PROM is more effective than ROM chips in regard to _______(a) Cost(b) Memory management(c) Speed of operation(d) Both Cost and Speed of operationThis question was addressed to me during an internship interview.The query is from Read-Only Memory topic in division Memory System of Computer Architecture
Answer» The CORRECT choice is (d) Both Cost and Speed of operation Best EXPLANATION: The PROM is cheaper than ROM as they can be PROGRAMMED MANUALLY.

Discussion

118.	The special communication used in RAMBUS are _________(a) RAMBUS channel(b) D-link(c) Dial-up(d) None of the mentionedThis question was posed to me by my school teacher while I was bunking the class.The question is from RamBus Memory topic in portion Memory System of Computer Architecture
Answer» The correct OPTION is (a) RAMBUS channel For explanation I would SAY: The special communication link is USED to provide the necessary design and required HARDWARE for the TRANSMISSION.

Discussion

119.	The processor must take into account the delay in accessing the memory location, such memories are called ______(a) Delay integrated(b) Asynchronous memories(c) Synchronous memories(d) Isochronous memoriesThe question was posed to me in an online quiz.My question is from Asynchronous DRAM topic in portion Memory System of Computer Architecture
Answer» CORRECT CHOICE is (b) ASYNCHRONOUS memories The explanation: None.

Discussion

120.	The bit used to signify that the cache location is updated is ________(a) Dirty bit(b) Update bit(c) Reference bit(d) Flag bitThis question was addressed to me during an interview for a job.This interesting question is from Caches topic in portion Memory System of Computer Architecture
Answer» Right OPTION is (a) Dirty BIT Best explanation: When the CACHE LOCATION is updated in order to signal to the PROCESSOR this bit is used.

Discussion

121.	While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for ________(a) Tag(b) Block(c) Word(d) IdI got this question in homework.My question is from Mapping Functions in chapter Memory System of Computer Architecture
Answer» Right answer is (a) TAG The best I can explain: The tag is used to IDENTIFY the block mapped onto ONE particular CACHE block.

Discussion

122.	The write-through procedure is used ________(a) To write onto the memory directly(b) To write and read from memory simultaneously(c) To write directly on the memory and the cache simultaneously(d) None of the mentionedThe question was posed to me during an internship interview.This is a very interesting question from Caches in division Memory System of Computer Architecture
Answer» Right choice is (c) To write DIRECTLY on the memory and the CACHE simultaneously For EXPLANATION I WOULD SAY: When write operation is issued then the corresponding operation is performed.

Discussion

123.	The spatial aspect of the locality of reference means ________(a) That the recently executed instruction is executed again next(b) That the recently executed won’t be executed again(c) That the instruction executed will be executed at a later time(d) That the instruction in close proximity of the instruction executed will be executed in futureThe question was posed to me in an interview.This intriguing question originated from Caches topic in chapter Memory System of Computer Architecture
Answer» Correct answer is (d) That the instruction in CLOSE proximity of the instruction executed will be executed in future Easiest explanation: The spatial aspect of locality of REFERENCE TELLS that the NEARBY instruction is more LIKELY to be executed in future.

Discussion

124.	The contents of the EPROM are erased by ________(a) Overcharging the chip(b) Exposing the chip to UV rays(c) Exposing the chip to IR rays(d) Discharging the ChipI have been asked this question in my homework.I need to ask this question from Read-Only Memory topic in division Memory System of Computer Architecture
Answer» The CORRECT ANSWER is (b) Exposing the chip to UV RAYS The explanation: To ERASE the contents of the EPROM the chip is exposed to the UV rays, which dissipate the charge on the TRANSISTOR.

Discussion

125.	The data is transferred over the RAMBUS as _______(a) Packets(b) Blocks(c) Swing voltages(d) BitsThe question was asked in an interview for job.This interesting question is from RamBus Memory topic in section Memory System of Computer Architecture
Answer» Right option is (C) Swing voltages To explain: By using voltage swings to TRANSFER data, the transfer RATE ALONG with EFFICIENCY is improved.

Discussion

126.	In order to read multiple bytes of a row at the same time, we make use of ______(a) Latch(b) Shift register(c) Cache(d) Memory extensionThe question was asked during an interview.My question is taken from Asynchronous DRAM topic in portion Memory System of Computer Architecture
Answer» Right answer is (a) Latch EASY EXPLANATION: The latch makes it easy to ready multiple bytes of data of the same row simultaneously by just giving the CONSECUTIVE column ADDRESS.

Discussion

127.	The disadvantage of DRAM over SRAM is/are _______(a) Lower data storage capacities(b) Higher heat dissipation(c) The cells are not static(d) All of the mentionedThe question was posed to me in final exam.This interesting question is from Asynchronous DRAM in chapter Memory System of Computer Architecture
Answer» The CORRECT ANSWER is (C) The cells are not static The EXPLANATION is: This means that the cells won’t hold their state indefinitely.

Discussion

128.	The advantage of CMOS SRAM over the transistor one’s is _________(a) Low cost(b) High efficiency(c) High durability(d) Low power consumptionThe question was posed to me at a job interview.The query is from Static Memories topic in division Memory System of Computer Architecture
Answer» The CORRECT CHOICE is (d) LOW power consumption Explanation: This is because the cell CONSUMES power only when it is being ACCESSED.

Discussion

129.	The flash memories find application in ______(a) Super computers(b) Mainframe systems(c) Distributed systems(d) Portable devicesI have been asked this question by my school teacher while I was bunking the class.I want to ask this question from Read-Only Memory in division Memory System of Computer Architecture
Answer» Right choice is (d) Portable DEVICES The best EXPLANATION: The flash MEMORIES low power requirement enables them to be USED in a wide RANGE of hand held devices.

Discussion

130.	The difference between the EPROM and ROM circuitry is _____(a) The usage of MOSFET’s over transistors(b) The usage of JFET’s over transistors(c) The usage of an extra transistor(d) None of the mentionedThis question was addressed to me in an online interview.My question comes from Read-Only Memory topic in division Memory System of Computer Architecture
Answer» The correct answer is (c) The usage of an EXTRA TRANSISTOR The best I can EXPLAIN: The EPROM uses an extra transistor where the GROUND CONNECTION is there in the ROM chip.

Discussion

131.	The address lines multiplexing is done using ______(a) MMU(b) Memory controller unit(c) Page table(d) Overlay generatorI got this question in an interview for job.This is a very interesting question from Large Memories in division Memory System of Computer Architecture
Answer» The correct ANSWER is (B) Memory CONTROLLER unit To explain I would say: This unit multiplexes the VARIOUS address lines to lesser pins on the chip.

Discussion

132.	The increase in operation speed is done by ________________(a) Reducing the reference voltage(b) Increasing the clk frequency(c) Using enhanced hardware(d) None of the mentionedThe question was posed to me by my school principal while I was bunking the class.The question is from RamBus Memory in section Memory System of Computer Architecture
Answer» The correct ANSWER is (a) REDUCING the reference VOLTAGE For explanation I would say: The reference voltage is reduced from the VSUPPLY about 2v.

Discussion

133.	To get the row address of the required data ______ is enabled.(a) CAS(b) RAS(c) CS(d) Sense/writeThis question was addressed to me during a job interview.I would like to ask this question from Asynchronous DRAM topic in division Memory System of Computer Architecture
Answer» The correct option is (B) RAS For EXPLANATION: This makes the CONTENTS of the row required REFRESHED.

Discussion

134.	In direct mapping the presence of the block in memory is checked with the help of block field.(a) True(b) FalseI have been asked this question in an interview for internship.The query is from Mapping Functions in portion Memory System of Computer Architecture
Answer» Right choice is (B) False The explanation is: The tag FIELD is USED to check the presence of a MEM BLOCK.

Discussion

135.	To reduce the number of external connections required, we make use of ______(a) De-multiplexer(b) Multiplexer(c) Encoder(d) DecoderThis question was posed to me in an international level competition.I'm obligated to ask this question of Asynchronous DRAM in section Memory System of Computer Architecture
Answer» Right CHOICE is (B) Multiplexer Easy EXPLANATION: We multiplex the various address lines ONTO fewer PINS.

Discussion

136.	The SDRAM performs operation on the _______(a) Rising edge of the clock(b) Falling edge of the clock(c) Middle state of the clock(d) Transition state of the clockThis question was addressed to me in an interview.The origin of the question is Synchronous DRAM topic in section Memory System of Computer Architecture
Answer» The CORRECT choice is (a) Rising edge of the clock To explain I WOULD SAY: The SDRAM’s are edge-triggered.

Discussion

137.	VLSI stands for ___________(a) Very Large Scale Integration(b) Very Large Stand-alone Integration(c) Volatile Layer System Interface(d) None of the mentionedThe question was asked during an online interview.The above asked question is from Static Memories in chapter Memory System of Computer Architecture
Answer» Correct CHOICE is (a) Very Large SCALE Integration For EXPLANATION: NONE.

Discussion

138.	The duration between the read and the mfc signal is ______(a) Access time(b) Latency(c) Delay(d) Cycle timeThis question was posed to me during an interview for a job.I want to ask this question from Static Memories topic in portion Memory System of Computer Architecture
Answer» The CORRECT option is (a) Access time The BEST I can EXPLAIN: The time between the issue of a read SIGNAL and the completion of it is called memory access time.

Discussion

139.	The key feature of the RAMBUS tech is ________(a) Greater memory utilisation(b) Efficiency(c) Speed of transfer(d) None of the mentionedThe question was asked during an online exam.Asked question is from RamBus Memory in section Memory System of Computer Architecture
Answer» Right OPTION is (c) Speed of transfer Explanation: The RAMBUS was DEVELOPED BASICALLY to lessen the DATA transfer time.

Discussion

140.	Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is ______(a) 0.0021(b) 0.0038(c) 0.0064(d) 0.0128The question was posed to me in quiz.I would like to ask this question from Large Memories in chapter Memory System of Computer Architecture
Answer» The correct answer is (b) 0.0038 To ELABORATE: The refresh OVERHEAD is calculated by taking into account the total time for refreshing and the INTERVAL of each refresh.

Discussion

141.	A _______ is used to restore the contents of the cells.(a) Sense amplifier(b) Refresh counter(c) Restorer(d) None of the mentionedThis question was posed to me in a national level competition.Origin of the question is Synchronous DRAM topic in chapter Memory System of Computer Architecture
Answer» Correct CHOICE is (B) Refresh COUNTER Explanation: The Counter helps to restore the CHARGE on the capacitor.

Discussion

142.	The reason for the cells to lose their state over time is ________(a) The lower voltage levels(b) Usage of capacitors to store the charge(c) Use of Shift registers(d) None of the mentionedI had been asked this question in an interview.My question is based upon Asynchronous DRAM topic in division Memory System of Computer Architecture
Answer» Right CHOICE is (b) Usage of CAPACITORS to STORE the charge To explain: Since capacitors are used the charge DISSIPATES over time.

Discussion

143.	A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into _____(a) 128 X 8(b) 256 X 4(c) 512 X 2(d) 1024 X 1I got this question in an online quiz.I'd like to ask this question from Static Memories in chapter Memory System of Computer Architecture
Answer» Correct choice is (d) 1024 X 1 For EXPLANATION I would say: All the others require LESS than 10 address BITS.

Discussion

144.	Circuits that can hold their state as long as power is applied is _______(a) Dynamic memory(b) Static memory(c) Register(d) CacheI have been asked this question in an internship interview.I need to ask this question from Static Memories in section Memory System of Computer Architecture
Answer» Correct CHOICE is (b) Static memory To EXPLAIN: NONE.

Discussion

145.	In associative mapping, in a 16 bit system the tag field has ______ bits.(a) 12(b) 8(c) 9(d) 10I have been asked this question in my homework.I'd like to ask this question from Mapping Functions in portion Memory System of Computer Architecture
Answer» CORRECT option is (a) 12 Explanation: The Tag field is used as an ID for the different memory BLOCKS MAPPED to the cache.

Discussion

146.	The minimum time delay between two successive memory read operations is ______(a) Cycle time(b) Latency(c) Delay(d) None of the mentionedThis question was addressed to me by my college director while I was bunking the class.I'm obligated to ask this question of Static Memories in chapter Memory System of Computer Architecture
Answer» CORRECT choice is (a) Cycle time The best explanation: The Time taken by the cpu to END ONE READ operation and to start one more is cycle time.

Discussion

147.	The effectiveness of the cache memory is based on the property of ________(a) Locality of reference(b) Memory localisation(c) Memory size(d) None of the mentionedThe question was asked during an internship interview.I want to ask this question from Caches topic in portion Memory System of Computer Architecture
Answer» CORRECT option is (a) Locality of reference Easy explanation: This MEANS that the CACHE depends on the location in the memory that is referenced often.

Discussion

148.	During a write operation if the required block is not present in the cache then ______ occurs.(a) Write latency(b) Write hit(c) Write delay(d) Write missThis question was addressed to me during an internship interview.Origin of the question is Mapping Functions in division Memory System of Computer Architecture
Answer» CORRECT choice is (d) Write miss The BEST explanation: This INDICATES that the OPERATION has MISSED and it brings the required block into the cache.

Discussion

149.	The reason for the implementation of the cache memory is ________(a) To increase the internal memory of the system(b) The difference in speeds of operation of the processor and memory(c) To reduce the memory access and cycle time(d) All of the mentionedI have been asked this question in exam.The question is from Caches topic in portion Memory System of Computer Architecture
Answer» Correct option is (b) The difference in speeds of OPERATION of the processor and memory The explanation is: This difference in the speeds of operation of the SYSTEM caused it to be INEFFICIENT.

Discussion

150.	The original design of the RAMBUS required for ________ data lines.(a) 4(b) 6(c) 8(d) 9I had been asked this question by my college director while I was bunking the class.The above asked question is from RamBus Memory topic in division Memory System of Computer Architecture
Answer» The correct choice is (d) 9 To ELABORATE: Out of the 9 data lines, 8 were used for data TRANSMISSION and the one left was used for parity CHECKING.

Discussion

Explore topic-wise InterviewSolutions in .

The RAS and CAS signals are provided by the ______(a) Mode register(b) CS(c) Memory controller(d) None of the mentionedThe question was posed to me in final exam.Question is from Large Memories topic in division Memory System of Computer Architecture

The higher order bits of the address are used to _____(a) Specify the row address(b) Specify the column address(c) Input the CS(d) None of the mentionedThe question was asked in semester exam.I'd like to ask this question from Large Memories topic in section Memory System of Computer Architecture

The controller multiplexes the addresses after getting the _____ signal.(a) INTR(b) ACK(c) RESET(d) RequestI got this question in homework.I need to ask this question from Large Memories in division Memory System of Computer Architecture

The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______(a) Memory sticks(b) Blue-ray devices(c) Flash memory(d) CMOSThis question was posed to me in an online interview.My query is from Read-Only Memory in portion Memory System of Computer Architecture

The logical addresses generated by the cpu are mapped onto physical memory by ____________(a) Relocation register(b) TLB(c) MMU(d) None of the mentionedThe question was asked in an interview for internship.The question is from Static Memories in portion Memory System of Computer Architecture

The ROM chips are mainly used to store _______(a) System files(b) Root directories(c) Boot files(d) Driver filesI had been asked this question in unit test.This intriguing question comes from Read-Only Memory topic in division Memory System of Computer Architecture

If the transistor gate is closed, then the ROM stores a value of 1.(a) True(b) FalseI had been asked this question in a job interview.My question is taken from Read-Only Memory topic in section Memory System of Computer Architecture

To organise large memory chips we make use of ______(a) Integrated chips(b) Upgraded hardware(c) Memory modules(d) None of the mentionedThis question was addressed to me in class test.The query is from Large Memories topic in division Memory System of Computer Architecture

In SDRAM’s buffers are used to store data that is read or written.(a) True(b) FalseI have been asked this question in semester exam.My doubt stems from Synchronous DRAM topic in section Memory System of Computer Architecture

The special communication used in RAMBUS are _________(a) RAMBUS channel(b) D-link(c) Dial-up(d) None of the mentionedThis question was posed to me by my school teacher while I was bunking the class.The question is from RamBus Memory topic in portion Memory System of Computer Architecture

The bit used to signify that the cache location is updated is ________(a) Dirty bit(b) Update bit(c) Reference bit(d) Flag bitThis question was addressed to me during an interview for a job.This interesting question is from Caches topic in portion Memory System of Computer Architecture

While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for ________(a) Tag(b) Block(c) Word(d) IdI got this question in homework.My question is from Mapping Functions in chapter Memory System of Computer Architecture

The data is transferred over the RAMBUS as _______(a) Packets(b) Blocks(c) Swing voltages(d) BitsThe question was asked in an interview for job.This interesting question is from RamBus Memory topic in section Memory System of Computer Architecture

In order to read multiple bytes of a row at the same time, we make use of ______(a) Latch(b) Shift register(c) Cache(d) Memory extensionThe question was asked during an interview.My question is taken from Asynchronous DRAM topic in portion Memory System of Computer Architecture

The advantage of CMOS SRAM over the transistor one’s is _________(a) Low cost(b) High efficiency(c) High durability(d) Low power consumptionThe question was posed to me at a job interview.The query is from Static Memories topic in division Memory System of Computer Architecture

The address lines multiplexing is done using ______(a) MMU(b) Memory controller unit(c) Page table(d) Overlay generatorI got this question in an interview for job.This is a very interesting question from Large Memories in division Memory System of Computer Architecture

To get the row address of the required data ______ is enabled.(a) CAS(b) RAS(c) CS(d) Sense/writeThis question was addressed to me during a job interview.I would like to ask this question from Asynchronous DRAM topic in division Memory System of Computer Architecture

In direct mapping the presence of the block in memory is checked with the help of block field.(a) True(b) FalseI have been asked this question in an interview for internship.The query is from Mapping Functions in portion Memory System of Computer Architecture

The duration between the read and the mfc signal is ______(a) Access time(b) Latency(c) Delay(d) Cycle timeThis question was posed to me during an interview for a job.I want to ask this question from Static Memories topic in portion Memory System of Computer Architecture

The key feature of the RAMBUS tech is ________(a) Greater memory utilisation(b) Efficiency(c) Speed of transfer(d) None of the mentionedThe question was asked during an online exam.Asked question is from RamBus Memory in section Memory System of Computer Architecture

A _______ is used to restore the contents of the cells.(a) Sense amplifier(b) Refresh counter(c) Restorer(d) None of the mentionedThis question was posed to me in a national level competition.Origin of the question is Synchronous DRAM topic in chapter Memory System of Computer Architecture

A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into _____(a) 128 X 8(b) 256 X 4(c) 512 X 2(d) 1024 X 1I got this question in an online quiz.I'd like to ask this question from Static Memories in chapter Memory System of Computer Architecture

Circuits that can hold their state as long as power is applied is _______(a) Dynamic memory(b) Static memory(c) Register(d) CacheI have been asked this question in an internship interview.I need to ask this question from Static Memories in section Memory System of Computer Architecture

In associative mapping, in a 16 bit system the tag field has ______ bits.(a) 12(b) 8(c) 9(d) 10I have been asked this question in my homework.I'd like to ask this question from Mapping Functions in portion Memory System of Computer Architecture

The original design of the RAMBUS required for ________ data lines.(a) 4(b) 6(c) 8(d) 9I had been asked this question by my college director while I was bunking the class.The above asked question is from RamBus Memory topic in division Memory System of Computer Architecture