88 + Interview Questions in Processor Families in Computer Architecture Page 1 InterviewSolution

1.	.data directive is used _________(a) To indicate the ending of the data section(b) To indicate the beginning of the data section(c) To declare all the source operands(d) To Initialize the operandsThe question was posed to me in semester exam.I would like to ask this question from Intel IA-32 Pentium Architecture-2 in chapter Processor Families of Computer Architecture
Answer» The correct choice is (b) To INDICATE the BEGINNING of the data section Explanation: This is USED to indicate the STARTING of the section of data.

Discussion

2.	The size of the floating registers can be extended upto _________(a) 128 bit(b) 256 bit(c) 80 bit(d) 64 bitThis question was posed to me by my school principal while I was bunking the class.My doubt is from Intel IA-32 Pentium Architecture-1 topic in section Processor Families of Computer Architecture
Answer» The correct answer is (c) 80 bit For EXPLANATION I WOULD say: NONE.

Discussion

3.	The __________ directive is used to allocate 4 bytes of memory.(a) DD(b) ALLOC(c) RESERVE(d) SPACEThis question was posed to me during an internship interview.Origin of the question is Intel IA-32 Pentium Architecture-2 in division Processor Families of Computer Architecture
Answer» The CORRECT OPTION is (a) DD The EXPLANATION is: NONE.

Discussion

4.	The addressing method used in IA-32 is ____________(a) Little Endian(b) Big Endian(c) X-Little Endian(d) Both Little and Big EndianI have been asked this question by my college director while I was bunking the class.My doubt is from Intel IA-32 Pentium Architecture-1 topic in division Processor Families of Computer Architecture
Answer» The correct OPTION is (a) Little Endian Easiest explanation: The METHOD of ADDRESSING the data in the SYSTEM.

Discussion

5.	The address system supported by ARM systems is/are ___________(a) Little Endian(b) Big Endian(c) X-Little Endian(d) Both Little & Big EndianI had been asked this question in examination.This intriguing question comes from ARM Architecture topic in division Processor Families of Computer Architecture
Answer» Correct option is (d) Both LITTLE & Big Endian The EXPLANATION: The way in which, the DATA gets stored in the system or the way of address allocation is called as address system.

Discussion

6.	ARM stands for _____________(a) Advanced Rate Machines(b) Advanced RISC Machines(c) Artificial Running Machines(d) Aviary Running MachinesThis question was addressed to me during an interview.This question is from ARM Architecture topic in section Processor Families of Computer Architecture
Answer» Right ANSWER is (B) Advanced RISC Machines Easiest explanation: ARM is a type of SYSTEM architecture.

Discussion

7.	The bit present in the op code, indicating which of the operands is the source is called as ________(a) SRC bit(b) Indirection bit(c) Direction bit(d) FRM bitI had been asked this question during an online interview.The origin of the question is Intel IA-32 Pentium Architecture-2 in chapter Processor Families of Computer Architecture
Answer» Correct CHOICE is (C) DIRECTION bit For explanation: NONE.

Discussion

8.	IOPL stands for ________(a) Input/Output Privilege level(b) Input Output Process Link(c) Internal Output Process Link(d) Internal Offset Privilege LevelI had been asked this question during an interview.This interesting question is from Intel IA-32 Pentium Architecture-1 in division Processor Families of Computer Architecture
Answer» Correct option is (a) Input/Output Privilege level The explanation: This INDICATES the security between the transfers between the I/O DEVICES and MEMORY.

Discussion

9.	The address space in ARM is ___________(a) 2^24(b) 2^64(c) 2^16(d) 2^32The question was posed to me by my school teacher while I was bunking the class.I'd like to ask this question from ARM Architecture topic in chapter Processor Families of Computer Architecture
Answer» CORRECT ANSWER is (d) 2^32 For EXPLANATION: NONE.

Discussion

10.	The instructions in 68000 can deal with operands of three different sizes.(a) True(b) FalseI have been asked this question during an internship interview.My question is from Motarola 680X0 Processor Architecture in section Processor Families of Computer Architecture
Answer» Correct OPTION is (a) True Explanation: The OPERANDS are of different SIZES because of the difference in the VALUES.

Discussion

11.	ARM processors where basically designed for _______(a) Main frame systems(b) Distributed systems(c) Mobile systems(d) Super computersThis question was posed to me in class test.This intriguing question originated from ARM Architecture in division Processor Families of Computer Architecture
Answer» RIGHT option is (c) Mobile systems The best EXPLANATION: These ARM processors are DESIGNED for HANDHELD DEVICES.

Discussion

12.	The bits used to indicate the status of the page in the memory is called ______(a) Control bits(b) Status bits(c) Progress bit(d) None of the mentionedThis question was posed to me during an interview.This interesting question is from Address Translation topic in division Processor Families of Computer Architecture
Answer» CORRECT choice is (a) Control bits Explanation: These bits are used to store the STATUS INFORMATION of the PROGRAM.

Discussion

13.	The higher order bits of the virtual address generated by the processor forms the _______(a) Table number(b) Frame number(c) List number(d) Page numberI got this question by my school teacher while I was bunking the class.My doubt is from Address Translation in portion Processor Families of Computer Architecture
Answer» The correct choice is (d) Page number Explanation: The HIGHER order BITS indicate the page number which POINTS to ONE particular entry in the page table.

Discussion

14.	The PC is incorporated with the help of general purpose registers.(a) True(b) FalseI had been asked this question in an internship interview.I'm obligated to ask this question of Intel IA-32 Pentium Architecture-1 in section Processor Families of Computer Architecture
Answer» Correct choice is (b) False Explanation: REGISTERS are not USED to INCORPORATE PC as in other architectures, but a SEPARATE space is ALLOCATED to it.

Discussion

15.	The condition to check whether the branch should happen or not is given by ____________(a) The lower order 8 bits of the instruction(b) The higher order 4 bits of the instruction(c) The lower order 4 bits of the instruction(d) The higher order 8 bits of the instructionThis question was addressed to me in a national level competition.This interesting question is from ARM Architecture topic in portion Processor Families of Computer Architecture
Answer» CORRECT CHOICE is (b) The higher order 4 bits of the instruction Easy explanation: None.

Discussion

16.	_________ instruction is used to get the 1’s complement of the operand.(a) COMP(b) BIC(c) ~CMP(d) MVNI had been asked this question in a national level competition.I'd like to ask this question from ARM Architecture topic in section Processor Families of Computer Architecture
Answer» The correct option is (d) MVN The best I can EXPLAIN: The COMPLEMENT of all the BITS of a data is its 1’s compliment.

Discussion

17.	As the instructions can deal with variable size operands we use ____________ to resolve this.(a) Delimiter(b) Size indicator mnemonic(c) Special assemblers(d) None of the mentionedThis question was addressed to me in final exam.My doubt is from Motarola 680X0 Processor Architecture topic in portion Processor Families of Computer Architecture
Answer» Right OPTION is (b) SIZE indicator mnemonic The explanation is: To INDICATE the size of the operand we USE a separate VARIABLE mnemonic to indicate it.

Discussion

18.	The 68000 has a max of how many data registers?(a) 16(b) 20(c) 10(d) 8I had been asked this question in a job interview.This intriguing question comes from Motorola 680X0 Processor Architecture in portion Processor Families of Computer Architecture
Answer» The correct OPTION is (d) 8 The EXPLANATION: The data registers are solely used for the purpose of STORING data ITEMS of the process.

Discussion

19.	Whenever a request to the page that is not present in the main memory is accessed ______ is triggered.(a) Interrupt(b) Request(c) Page fault(d) None of the mentionedThe question was posed to me in unit test.The origin of the question is Address Translation topic in chapter Processor Families of Computer Architecture
Answer» Correct answer is (C) PAGE fault Explanation: When a page fault is triggered, the OS brings the required page into MEMORY.

Discussion

20.	The page table should be ideally situated within ____________(a) Processor(b) TLB(c) MMU(d) CacheThe question was posed to me in an online interview.I'm obligated to ask this question of Address Translation in portion Processor Families of Computer Architecture
Answer» Correct answer is (c) MMU To elaborate: The PAGE table information is USED for EVERY READ and ACCESS operation.

Discussion

21.	The _______ bit is used to indicate the validity of the page.(a) Valid bit(b) Invalid bit(c) Correct bit(d) None of the mentionedI had been asked this question during an internship interview.This intriguing question comes from Address Translation topic in division Processor Families of Computer Architecture
Answer» Correct choice is (a) VALID bit The best I can explain: The OS FIRST validates the page and then only MOVES from the page table.

Discussion

22.	The instruction, ADD R1, R2, R3 is decoded as ___________(a) R1
Answer» CORRECT OPTION is (d) R1<-[R2]+[R3] The EXPLANATION is: None.

Discussion

23.	___________ directive is used to name the register used for execution of an instruction.(a) ASSIGN(b) RN(c) NAME(d) DECLAREI have been asked this question in semester exam.The query is from ARM Architecture in section Processor Families of Computer Architecture
Answer» Right option is (B) RN Easy EXPLANATION: This INSTRUCTION is used to LIST the registers used for execution.

Discussion

24.	The instruction, MLA R0,R1,R2,R3performs _________(a) R0
Answer» RIGHT CHOICE is (c) R0<-[R1]*[R2]+[R3] Explanation: The MLA instruction is used PERFORM ADDITION and multiplication together.

Discussion

25.	__________ directive is used to indicate the beginning of the program instruction or data.(a) EQU(b) START(c) AREA(d) SPACEThis question was posed to me during a job interview.My doubt is from ARM Architecture topic in chapter Processor Families of Computer Architecture
Answer» CORRECT OPTION is (C) AREA Easiest EXPLANATION: NONE.

Discussion

26.	The instructions which are used to load or store multiple operands are called as __________(a) Banked instructions(b) Lump transfer instructions(c) Block transfer instructions(d) DMA instructionsThis question was addressed to me during an interview.My question is from ARM Architecture in portion Processor Families of Computer Architecture
Answer» RIGHT ANSWER is (c) Block TRANSFER INSTRUCTIONS Explanation: These instructions are generally used to PERFORM memory transfer operations.

Discussion

27.	The Bit extension of the register is denoted with the help of __________ symbol.(a) (dollarSign)(b) `(c) E(d) ~The question was posed to me in an interview.I'm obligated to ask this question of Intel IA-32 Pentium Architecture-1 topic in chapter Processor Families of Computer Architecture
Answer» RIGHT OPTION is (c) E Explanation: This is USED to extend the SIZE of the REGISTER.

Discussion

28.	The BEQ instructions is used ____________(a) To check the equality condition between the operands and then branch(b) To check if the Operand is greater than the condition value and then branch(c) To check if the flag Z is set to 1 and then causes branch(d) None of the mentionedThe question was posed to me during an internship interview.Query is from ARM Architecture in portion Processor Families of Computer Architecture
Answer» CORRECT option is (c) To check if the flag Z is SET to 1 and then CAUSES BRANCH The best I can explain: This INSTRUCTION is basically used to check the branch enable bit.

Discussion

29.	The word length in the 68000 computer is _______(a) 32 bit(b) 64 bit(c) 16 bit(d) 8 bitI had been asked this question in a national level competition.The doubt is from Motorola 680X0 Processor Architecture topic in chapter Processor Families of Computer Architecture
Answer» Right CHOICE is (C) 16 bit The explanation is: The LENGTH of an instruction that can be read or accessed at a TIME is REFERRED to as word length.

Discussion

30.	The addressing mode where the EA of the operand is the contents of Rn is ______(a) Pre-indexed mode(b) Pre-indexed with write back mode(c) Post-indexed mode(d) None of the mentionedThe question was asked at a job interview.My question is based upon ARM Architecture in section Processor Families of Computer Architecture
Answer» The CORRECT CHOICE is (C) Post-indexed mode To ELABORATE: NONE.

Discussion

31.	RISC stands for _________(a) Restricted Instruction Sequencing Computer(b) Restricted Instruction Sequential Compiler(c) Reduced Instruction Set Computer(d) Reduced Induction Set ComputerI had been asked this question in an online quiz.I'm obligated to ask this question of ARM Architecture in division Processor Families of Computer Architecture
Answer» The CORRECT ANSWER is (c) REDUCED INSTRUCTION Set Computer Explanation: This is a SYSTEM architecture, in which the performance of the system is improved by reducing the size of the instruction set.

Discussion

32.	The 68000 uses ____________ method to access I/O devices buffers.(a) Memory mapped(b) I/O mapped(c) Buffer mapped(d) None of the mentionedThe question was posed to me in my homework.My question is based upon Motarola 680X0 Processor Architecture topic in chapter Processor Families of Computer Architecture
Answer» Correct ANSWER is (a) MEMORY mapped Best EXPLANATION: In this method, both the I/O device and the memory SHARE a common address SPACE.

Discussion

33.	The TLB is incorporated as part of the _________(a) Processor(b) MMU(c) Disk(d) RAMThe question was posed to me in a job interview.Question is taken from Address Translation in section Processor Families of Computer Architecture
Answer» The CORRECT OPTION is (B) MMU To EXPLAIN: NONE.

Discussion

34.	In case of multimedia extension instructions, the pixels are encoded into a data item of _________(a) 16 bit(b) 32 bit(c) 24 bit(d) 8 bitI got this question during an interview.My query is from Intel IA-32 Pentium Architecture-2 topic in division Processor Families of Computer Architecture
Answer» Right option is (d) 8 bit To EXPLAIN I would SAY: NONE.

Discussion

35.	The status register of the 68000 has ____ condition codes.(a) 7(b) 4(c) 5(d) 8This question was addressed to me by my college director while I was bunking the class.Asked question is from Motorola 680X0 Processor Architecture in portion Processor Families of Computer Architecture
Answer» Right choice is (C) 5 To EXPLAIN I would say: The register which is USED to basically STORE the condition FLAGS is called as a status register.

Discussion

36.	Each instruction in ARM machines is encoded into __________ Word.(a) 2 byte(b) 3 byte(c) 4 byte(d) 8 byteThe question was asked during an interview.This question is from ARM Architecture topic in division Processor Families of Computer Architecture
Answer» The correct answer is (C) 4 byte To explain I would say: The DATA is encrypted to MAKE them secure.

Discussion

37.	Is 68000 computer Byte addressable?(a) True(b) FalseI have been asked this question in homework.My question is taken from Motorola 680X0 Processor Architecture in section Processor Families of Computer Architecture
Answer» The correct choice is (a) True The BEST EXPLANATION: The ability of a system to access the entire DATA of a process by reading consecutive bytes is called as BYTE addressability

Discussion

38.	The area in the main memory that can hold one page is called as ___________(a) Page entry(b) Page frame(c) Frame(d) BlockI had been asked this question in final exam.The above asked question is from Address Translation in chapter Processor Families of Computer Architecture
Answer» The CORRECT option is (B) PAGE frame The best I can EXPLAIN: None.

Discussion

39.	The lower order bits of the virtual address forms the __________(a) Page number(b) Frame number(c) Block number(d) OffsetThis question was posed to me during an online interview.This intriguing question comes from Address Translation in chapter Processor Families of Computer Architecture
Answer» The correct ANSWER is (d) OFFSET For EXPLANATION: This gives the offset within the page table.

Discussion

40.	SIMD stands for __________(a) Single Instruction Multiple Data(b) Simple Instruction Multiple Decoding(c) Sequential Instruction Multiple Decoding(d) System Information Mutable DataI had been asked this question in homework.Question is from Intel IA-32 Pentium Architecture-2 topic in chapter Processor Families of Computer Architecture
Answer» Right answer is (a) SINGLE INSTRUCTION Multiple DATA Explanation: This is the instruction USED to PERFORM an operation on multiple types of data.

Discussion

41.	The instruction used to multiply operands yielding a double integer outcome is _________(a) MUL(b) IMUL(c) DMUL(d) EMULThe question was posed to me by my college professor while I was bunking the class.This question is from Intel IA-32 Pentium Architecture-2 topic in section Processor Families of Computer Architecture
Answer» Correct choice is (b) IMUL The explanation is: This instruction is used to CARRY out multiplication on LARGE integral VALUES.

Discussion

42.	The Instruction, LDM R10!, {R0,R1,R6,R7}______(a) Loads the contents of R10 into R1, R0, R6 and R7(b) Creates a copy of the contents of R10 in the other registers except for the above mentioned ones(c) Loads the contents of the registers R1, R0, R6 and R7 to R10(d) Writes the contents of R10 into the above mentioned registers and clears R10I got this question in a job interview.I'm obligated to ask this question of ARM Architecture in division Processor Families of Computer Architecture
Answer» The correct answer is (a) LOADS the CONTENTS of R10 into R1, R0, R6 and R7 Best explanation: The LDM instruction is used to load DATA into multiple LOCATIONS.

Discussion

43.	__________ instruction is used to check the bit of the condition flags.(a) TEST(b) TB(c) CHECK(d) BTThis question was addressed to me in an interview.Question is from Intel IA-32 Pentium Architecture-2 in portion Processor Families of Computer Architecture
Answer» Correct option is (d) BT Easy EXPLANATION: This is USED to CHECK the CONDITION flags for exceptions.

Discussion

44.	___________ symbol is used to signify write back mode.(a) #(b) ^(c) &(d) !I have been asked this question during an interview.This is a very interesting question from ARM Architecture topic in section Processor Families of Computer Architecture
Answer» The CORRECT CHOICE is (d) ! EASY EXPLANATION: NONE.

Discussion

45.	_____ register is designated to point to the 68000 processor stack.(a) A7 register(b) B2 register(c) There is no such designation(d) Any general purpose register is selected at randomThis question was posed to me during an internship interview.Enquiry is from Motorola 680X0 Processor Architecture in section Processor Families of Computer Architecture
Answer» Correct answer is (a) A7 register The explanation is: The PROCESSOR stack is the PLACE USED to STORE the ongoing and upcoming PROCESS information

Discussion

46.	____________ instruction is used to set up a frame pointer for the subroutines in 68000.(a) CREATE(b) LINK(c) UNLK(d) FRAMEThe question was posed to me in an online interview.The above asked question is from Motarola 680X0 Processor Architecture topic in division Processor Families of Computer Architecture
Answer» The CORRECT answer is (B) LINK The EXPLANATION: This POINTER is used to monitor the stack.

Discussion

47.	The offset used in the conditional branching is __________ bit.(a) 24(b) 32(c) 16(d) 8The question was posed to me in my homework.I need to ask this question from ARM Architecture topic in division Processor Families of Computer Architecture
Answer» Right choice is (a) 24 Best EXPLANATION: The OFFSET is used to get the new BRANCHING ADDRESS of the process.

Discussion

48.	If the page table is large then it is stored in __________(a) Processor(b) Main memory(c) Disk(d) Secondary storageThe question was posed to me during an interview for a job.This interesting question is from Address Translation in section Processor Families of Computer Architecture
Answer» The correct choice is (b) Main memory Explanation: By STORING the table on the RAM the REQUIRED OPERATION’s speed is increased.

Discussion

49.	The Branch instruction in 68000 provides how many types of offsets?(a) 3(b) 1(c) 0(d) 2The question was posed to me in a job interview.Query is from Motarola 680X0 Processor Architecture in section Processor Families of Computer Architecture
Answer» RIGHT choice is (d) 2 Explanation: The Branch instruction basically just ADDS a constant VALUE to the address present in the PC, to change the instruction to be EXECUTED.

Discussion

50.	The memory allocated to each page is contiguous.(a) True(b) FalseThe question was asked during a job interview.I would like to ask this question from Address Translation topic in section Processor Families of Computer Architecture
Answer» Correct choice is (a) True Best EXPLANATION: Each page MIGHT be allocated MEMORY DEFERENTIALLY but the memory for one page will be continuous.

Discussion

Explore topic-wise InterviewSolutions in .

The __________ directive is used to allocate 4 bytes of memory.(a) DD(b) ALLOC(c) RESERVE(d) SPACEThis question was posed to me during an internship interview.Origin of the question is Intel IA-32 Pentium Architecture-2 in division Processor Families of Computer Architecture

ARM stands for _____________(a) Advanced Rate Machines(b) Advanced RISC Machines(c) Artificial Running Machines(d) Aviary Running MachinesThis question was addressed to me during an interview.This question is from ARM Architecture topic in section Processor Families of Computer Architecture

The address space in ARM is ___________(a) 2^24(b) 2^64(c) 2^16(d) 2^32The question was posed to me by my school teacher while I was bunking the class.I'd like to ask this question from ARM Architecture topic in chapter Processor Families of Computer Architecture

The instructions in 68000 can deal with operands of three different sizes.(a) True(b) FalseI have been asked this question during an internship interview.My question is from Motarola 680X0 Processor Architecture in section Processor Families of Computer Architecture

ARM processors where basically designed for _______(a) Main frame systems(b) Distributed systems(c) Mobile systems(d) Super computersThis question was posed to me in class test.This intriguing question originated from ARM Architecture in division Processor Families of Computer Architecture

The PC is incorporated with the help of general purpose registers.(a) True(b) FalseI had been asked this question in an internship interview.I'm obligated to ask this question of Intel IA-32 Pentium Architecture-1 in section Processor Families of Computer Architecture

_________ instruction is used to get the 1’s complement of the operand.(a) COMP(b) BIC(c) ~CMP(d) MVNI had been asked this question in a national level competition.I'd like to ask this question from ARM Architecture topic in section Processor Families of Computer Architecture

The 68000 has a max of how many data registers?(a) 16(b) 20(c) 10(d) 8I had been asked this question in a job interview.This intriguing question comes from Motorola 680X0 Processor Architecture in portion Processor Families of Computer Architecture

The page table should be ideally situated within ____________(a) Processor(b) TLB(c) MMU(d) CacheThe question was posed to me in an online interview.I'm obligated to ask this question of Address Translation in portion Processor Families of Computer Architecture

The instruction, ADD R1, R2, R3 is decoded as ___________(a) R1

___________ directive is used to name the register used for execution of an instruction.(a) ASSIGN(b) RN(c) NAME(d) DECLAREI have been asked this question in semester exam.The query is from ARM Architecture in section Processor Families of Computer Architecture

The instruction, MLA R0,R1,R2,R3performs _________(a) R0

__________ directive is used to indicate the beginning of the program instruction or data.(a) EQU(b) START(c) AREA(d) SPACEThis question was posed to me during a job interview.My doubt is from ARM Architecture topic in chapter Processor Families of Computer Architecture

The Bit extension of the register is denoted with the help of __________ symbol.(a) (dollarSign)(b) `(c) E(d) ~The question was posed to me in an interview.I'm obligated to ask this question of Intel IA-32 Pentium Architecture-1 topic in chapter Processor Families of Computer Architecture

The word length in the 68000 computer is _______(a) 32 bit(b) 64 bit(c) 16 bit(d) 8 bitI had been asked this question in a national level competition.The doubt is from Motorola 680X0 Processor Architecture topic in chapter Processor Families of Computer Architecture

The TLB is incorporated as part of the _________(a) Processor(b) MMU(c) Disk(d) RAMThe question was posed to me in a job interview.Question is taken from Address Translation in section Processor Families of Computer Architecture

In case of multimedia extension instructions, the pixels are encoded into a data item of _________(a) 16 bit(b) 32 bit(c) 24 bit(d) 8 bitI got this question during an interview.My query is from Intel IA-32 Pentium Architecture-2 topic in division Processor Families of Computer Architecture

The status register of the 68000 has ____ condition codes.(a) 7(b) 4(c) 5(d) 8This question was addressed to me by my college director while I was bunking the class.Asked question is from Motorola 680X0 Processor Architecture in portion Processor Families of Computer Architecture

Each instruction in ARM machines is encoded into __________ Word.(a) 2 byte(b) 3 byte(c) 4 byte(d) 8 byteThe question was asked during an interview.This question is from ARM Architecture topic in division Processor Families of Computer Architecture

Is 68000 computer Byte addressable?(a) True(b) FalseI have been asked this question in homework.My question is taken from Motorola 680X0 Processor Architecture in section Processor Families of Computer Architecture

The area in the main memory that can hold one page is called as ___________(a) Page entry(b) Page frame(c) Frame(d) BlockI had been asked this question in final exam.The above asked question is from Address Translation in chapter Processor Families of Computer Architecture

The lower order bits of the virtual address forms the __________(a) Page number(b) Frame number(c) Block number(d) OffsetThis question was posed to me during an online interview.This intriguing question comes from Address Translation in chapter Processor Families of Computer Architecture

__________ instruction is used to check the bit of the condition flags.(a) TEST(b) TB(c) CHECK(d) BTThis question was addressed to me in an interview.Question is from Intel IA-32 Pentium Architecture-2 in portion Processor Families of Computer Architecture

___________ symbol is used to signify write back mode.(a) #(b) ^(c) &(d) !I have been asked this question during an interview.This is a very interesting question from ARM Architecture topic in section Processor Families of Computer Architecture

The offset used in the conditional branching is __________ bit.(a) 24(b) 32(c) 16(d) 8The question was posed to me in my homework.I need to ask this question from ARM Architecture topic in division Processor Families of Computer Architecture

If the page table is large then it is stored in __________(a) Processor(b) Main memory(c) Disk(d) Secondary storageThe question was posed to me during an interview for a job.This interesting question is from Address Translation in section Processor Families of Computer Architecture

The Branch instruction in 68000 provides how many types of offsets?(a) 3(b) 1(c) 0(d) 2The question was posed to me in a job interview.Query is from Motarola 680X0 Processor Architecture in section Processor Families of Computer Architecture

The memory allocated to each page is contiguous.(a) True(b) FalseThe question was asked during a job interview.I would like to ask this question from Address Translation topic in section Processor Families of Computer Architecture