181 + Interview Questions in Input Output Organisation in Computer Architecture Page 1 InterviewSolution

1.	The BSY signal signifies _________(a) The BUs is busy(b) The controller is busy(c) The Initiator is busy(d) The Target is BusyI got this question during an interview for a job.I'd like to ask this question from SCSI BUS-1 topic in portion Input/Output Organisation of Computer Architecture
Answer» Right ANSWER is (a) The BUs is busy The explanation: This SIGNAL is generally INITIATED when the BUS is currently OCCUPIED in an operation.

Discussion

2.	In a data transfer operation involving SCSI BUS, the control is with ______(a) Initiator(b) Target(c) SCSI controller(d) Target ControllerThe question was posed to me in semester exam.My doubt is from SCSI BUS-1 topic in chapter Input/Output Organisation of Computer Architecture
Answer» The CORRECT option is (d) Target Controller To explain: The INITIATOR involves in the arbitration process and after winning the BUS it’ll hand over the CONTROL to the target controller.

Discussion

3.	The signal used to initiate device select ________(a) IRDY#(b) S/BE(c) DEVSEL#(d) IDSEL#This question was addressed to me by my college director while I was bunking the class.I'm obligated to ask this question of PCI BUS-2 topic in chapter Input/Output Organisation of Computer Architecture
Answer» RIGHT answer is (d) IDSEL# Easiest EXPLANATION: This signal is used to INITIALIZATION of DEVICE SELECT.

Discussion

4.	The PCI BUS has _____ interrupt request lines.(a) 6(b) 1(c) 4(d) 3This question was addressed to me in an interview for internship.The doubt is from PCI BUS-2 in portion Input/Output Organisation of Computer Architecture
Answer» CORRECT answer is (c) 4 The BEST EXPLANATION: The interrupt request LINES are used by the DEVICES connected to raise the interrupts.

Discussion

5.	To overcome the conflict over the possession of the BUS we use ______(a) Optimizers(b) BUS arbitrators(c) Multiple BUS structure(d) None of the mentionedThis question was posed to me during an interview.This is a very interesting question from Direct Memory Access topic in section Input/Output Organisation of Computer Architecture
Answer» Correct answer is (b) BUS arbitrators Easy EXPLANATION: The BUS arbitrator is USED to OVERCOME the contention over the BUS possession.

Discussion

6.	What is the full form of ANSI?(a) American National Standards Institute(b) Architectural National Standards Institute(c) Asian National Standards Institute(d) None of the mentionedThis question was posed to me in unit test.My question is taken from Standard I/O Interfaces topic in portion Input/Output Organisation of Computer Architecture
Answer» Correct ANSWER is (a) AMERICAN NATIONAL Standards Institute Explanation: The ANSI is ONE of the standard architecture USED by companies in designing the systems.

Discussion

7.	The technique whereby the DMA controller steals the access cycles of the processor to operate is called __________(a) Fast conning(b) Memory Con(c) Cycle stealing(d) Memory stealingI have been asked this question by my college director while I was bunking the class.Question is taken from Direct Memory Access in portion Input/Output Organisation of Computer Architecture
Answer» Right option is (c) CYCLE stealing To explain: The CONTROLLER takes over the processor’s ACCESS CYCLES and performs memory OPERATIONS.

Discussion

8.	The DMA differs from the interrupt mode by __________(a) The involvement of the processor for the operation(b) The method of accessing the I/O devices(c) The amount of data transfer possible(d) None of the mentionedI have been asked this question in examination.Origin of the question is Direct Memory Access in chapter Input/Output Organisation of Computer Architecture
Answer» Right OPTION is (d) NONE of the mentioned The explanation: DMA is an APPROACH of performing data transfers in bulk between memory and the EXTERNAL device WITHOUT the intervention of the processor.

Discussion

9.	Interrupts form an important part of _____ systems.(a) Batch processing(b) Multitasking(c) Real-time processing(d) Multi-userThe question was asked in exam.This question is from Interrupts in chapter Input/Output Organisation of Computer Architecture
Answer» RIGHT ANSWER is (c) Real-time processing The explanation is: This forms an important part of the Real time SYSTEM since if a PROCESS arrives with greater PRIORITY then it raises an interrupt and the other process is stopped and the interrupt will be serviced.

Discussion

10.	In vectored interrupts, how does the device identify itself to the processor?(a) By sending its device id(b) By sending the machine code for the interrupt service routine(c) By sending the starting address of the service routine(d) None of the mentionedI got this question in an interview.Question is taken from Interrupts in section Input/Output Organisation of Computer Architecture
Answer» RIGHT CHOICE is (c) By sending the starting address of the SERVICE routine To explain: By sending the starting address of the routine the device IDS the routine required and thereby IDENTIFYING itself.

Discussion

11.	The interrupt-request line is a part of the ___________(a) Data line(b) Control line(c) Address line(d) None of the mentionedI got this question during an interview.My question is from Interrupts in division Input/Output Organisation of Computer Architecture
Answer» Correct option is (b) Control line The best EXPLANATION: The Interrupt-request line is a control line along which the device is ALLOWED to SEND the interrupt signal.

Discussion

12.	The data packets can contain data upto ______(a) 512 bytes(b) 256 bytes(c) 1024 bytes(d) 2 KBThis question was posed to me during a job interview.I want to ask this question from USB in division Input/Output Organisation of Computer Architecture
Answer» The correct OPTION is (C) 1024 bytes To explain: NONE.

Discussion

13.	The PCI BUS supports _____ address space/s.(a) I/O(b) Memory(c) Configuration(d) All of the mentionedThis question was posed to me at a job interview.My question comes from PCI BUS-1 in section Input/Output Organisation of Computer Architecture
Answer» CORRECT option is (d) All of the mentioned Best explanation: The PCI BUS is mainly built to PROVIDE a WIDE range of connectivity for devices.

Discussion

14.	The PCI follows a set of standards primarily used in _____ PC’s.(a) Intel(b) Motorola(c) IBM(d) SUNThe question was asked in unit test.My question is taken from PCI BUS-1 topic in division Input/Output Organisation of Computer Architecture
Answer» RIGHT option is (c) IBM For explanation I WOULD say: The PCI BUS has a CLOSER resemblance to IBM architecture.

Discussion

15.	The Status flag circuit is implemented using _____(a) RS flip flop(b) D flip flop(c) JK flip flop(d) Xor circuitThis question was addressed to me in semester exam.This is a very interesting question from Parallel Port topic in chapter Input/Output Organisation of Computer Architecture
Answer» The correct CHOICE is (B) D FLIP flop To explain I would SAY: The circuit is implemented using the edge triggered D flip flop, that is triggered on the rising edge of the valid SIGNAL.

Discussion

16.	Which is fed into the BUS first by the initiator?(a) Data(b) Address(c) Commands or controls(d) Address, Commands or controlsThis question was addressed to me in exam.The question is from Synchronous BUS topic in division Input/Output Organisation of Computer Architecture
Answer» CORRECT ANSWER is (d) ADDRESS, COMMANDS or controls Explanation: NONE.

Discussion

17.	The device which starts data transfer is called __________(a) Master(b) Transactor(c) Distributor(d) InitiatorThis question was addressed to me in an interview for job.This question is from Synchronous BUS topic in section Input/Output Organisation of Computer Architecture
Answer» Correct answer is (d) Initiator To ELABORATE: The device which STARTS the DATA TRANSFER is CALLED an initiator.

Discussion

18.	In Distributed arbitration, the device requesting the BUS ______(a) Asserts the Start arbitration signal(b) Sends an interrupt signal(c) Sends an acknowledge signal(d) None of the mentionedThis question was posed to me at a job interview.Asked question is from Bus Arbitration in portion Input/Output Organisation of Computer Architecture
Answer» Correct ANSWER is (a) ASSERTS the Start arbitration signal Best EXPLANATION: None.

Discussion

19.	Once the BUS is granted to a device ___________(a) It activates the BUS busy line(b) Performs the required operation(c) Raises an interrupt(d) All of the mentionedI had been asked this question in an internship interview.My enquiry is from Bus Arbitration topic in chapter Input/Output Organisation of Computer Architecture
Answer» The correct OPTION is (a) It activates the BUS busy line The best I can EXPLAIN: The BUS busy activated indicates that the BUS is ALREADY ALLOCATED to a device and is being used.

Discussion

20.	The circuit used for the request line is a _________(a) Open-collector(b) EX-OR circuit(c) Open-drain(d) Nand circuitThis question was addressed to me in my homework.The origin of the question is Bus Arbitration in section Input/Output Organisation of Computer Architecture
Answer» The correct OPTION is (C) Open-drain The best EXPLANATION: None.

Discussion

21.	The registers of the controller are ______(a) 64 bits(b) 24 bits(c) 32 bits(d) 16 bitsI had been asked this question in an international level competition.This question is from Direct Memory Access topic in division Input/Output Organisation of Computer Architecture
Answer» Correct option is (C) 32 bits The BEST explanation: None.

Discussion

22.	The time between the receiver of an interrupt and its service is ______(a) Interrupt delay(b) Interrupt latency(c) Cycle time(d) Switching timeThis question was addressed to me at a job interview.This intriguing question originated from Interrupts topic in portion Input/Output Organisation of Computer Architecture
Answer» The correct answer is (B) Interrupt latency For explanation I would say: The delay in servicing of an interrupt happens DUE to the time is taken for contact SWITCH to take place.

Discussion

23.	The usual BUS structure used to connect the I/O devices is ___________(a) Star BUS structure(b) Multiple BUS structure(c) Single BUS structure(d) Node to Node BUS structureThe question was asked in unit test.The question is from Accessing I/O Devices in chapter Input/Output Organisation of Computer Architecture
Answer» Right option is (c) SINGLE BUS structure The best EXPLANATION: BUS is a collection of address, CONTROL and data LINES used to CONNECT the various devices of the computer.

Discussion

24.	The 4 bit PID’s are transmitted twice.(a) True(b) FalseThis question was addressed to me in my homework.I want to ask this question from USB in portion Input/Output Organisation of Computer Architecture
Answer» Right answer is (a) TRUE Explanation: The fields are transmitted TWICE, once with the true VALUES and the second TIME with the complemented values.

Discussion

25.	The high speed mode of operation of the USB was introduced by _____(a) ISA(b) USB 3.0(c) USB 2.0(d) ANSIThis question was addressed to me in an international level competition.The doubt is from USB topic in chapter Input/Output Organisation of Computer Architecture
Answer» Correct OPTION is (c) USB 2.0 The BEST EXPLANATION: The high-speed mode of operation was INTRODUCED with USB 2.0, which enabled the USB to operate at 480 Mb/s.

Discussion

26.	The transfer rate, when the USB is operating in low-speed of operation is _____(a) 5 Mb/s(b) 12 Mb/s(c) 2.5 Mb/s(d) 1.5 Mb/sThis question was posed to me in final exam.This intriguing question originated from USB in portion Input/Output Organisation of Computer Architecture
Answer» CORRECT OPTION is (d) 1.5 Mb/s Explanation: The USB has two RATES of operation the low-speed and the full-speed one.

Discussion

27.	______ is used as an intermediate to extend the processor BUS.(a) Bridge(b) Router(c) Connector(d) GatewayThis question was addressed to me in semester exam.I need to ask this question from Standard I/O Interfaces topic in section Input/Output Organisation of Computer Architecture
Answer» CORRECT choice is (a) Bridge Easy EXPLANATION: The bridge circuit is basically used to extend the processor BUS to connect DEVICES.

Discussion

28.	When the processor receives the request from a device, it responds by sending _____(a) Acknowledge signal(b) BUS grant signal(c) Response signal(d) None of the mentionedThe question was asked in my homework.My question is from Bus Arbitration in division Input/Output Organisation of Computer Architecture
Answer» Right choice is (b) BUS grant SIGNAL To EXPLAIN I would SAY: The Grant signal is PASSED from one device to the other until the device that has requested is found.

Discussion

29.	The DMA transfers are performed by a control circuit called as __________(a) Device interface(b) DMA controller(c) Data controller(d) OverlookerThe question was asked in semester exam.My query is from Direct Memory Access in division Input/Output Organisation of Computer Architecture
Answer» The CORRECT ANSWER is (b) DMA CONTROLLER Best EXPLANATION: The Controller performs the functions that would normally be CARRIED out by the processor.

Discussion

30.	After the completion of the DMA transfer, the processor is notified by __________(a) Acknowledge signal(b) Interrupt signal(c) WMFC signal(d) None of the mentionedThis question was addressed to me in an online quiz.The origin of the question is Direct Memory Access topic in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT ANSWER is (b) Interrupt SIGNAL Explanation: The CONTROLLER raises an interrupt signal to notify the processor that the transfer was complete.

Discussion

31.	The instructions which can be run only supervisor mode are?(a) Non-privileged instructions(b) System instructions(c) Privileged instructions(d) Exception instructionsI had been asked this question in semester exam.This question is from Exceptions topic in division Input/Output Organisation of Computer Architecture
Answer» Correct answer is (C) Privileged instructions The explanation: These instructions are those which can are crucial for the system’s performance and hence cannot be adultered by USER programs, so is RUN only in SUPERVISOR MODE.

Discussion

32.	The program used to find out errors is called __________(a) Debugger(b) Compiler(c) Assembler(d) ScannerI had been asked this question by my school teacher while I was bunking the class.The query is from Exceptions in section Input/Output Organisation of Computer Architecture
Answer» RIGHT option is (a) Debugger The explanation is: Debugger is a program USED to DETECT and CORRECT ERRORS in the program.

Discussion

33.	The return address from the interrupt-service routine is stored on the ___________(a) System heap(b) Processor register(c) Processor stack(d) MemoryThe question was posed to me during an internship interview.I'd like to ask this question from Interrupts in section Input/Output Organisation of Computer Architecture
Answer» Correct choice is (c) Processor STACK For explanation I WOULD say: The Processor after servicing the INTERRUPTS as to load the address of the previous PROCESS and this address is stored in the stack.

Discussion

34.	The method of accessing the I/O devices by repeatedly checking the status flags is ___________(a) Program-controlled I/O(b) Memory-mapped I/O(c) I/O mapped(d) None of the mentionedThis question was posed to me in a national level competition.This interesting question is from Accessing I/O Devices in division Input/Output Organisation of Computer Architecture
Answer» Correct CHOICE is (a) Program-controlled I/O Easy EXPLANATION: In this method, the PROCESSOR constantly CHECKS the STATUS flags, and when it finds that the flag is set it performs the appropriate operation.

Discussion

35.	______ interrupt method uses register whose bits are set separately by interrupt signal for each device.(a) Parallel priority interrupt(b) Serial priority interrupt(c) Daisy chaining(d) None of the mentionedI have been asked this question in class test.The question is from Interrupts in portion Input/Output Organisation of Computer Architecture
Answer» RIGHT ANSWER is (a) Parallel PRIORITY interrupt For explanation: None.

Discussion

36.	The last field in the packet is ______(a) PID(b) ADDR(c) ENDP(d) CRCI have been asked this question during a job interview.This intriguing question comes from USB topic in section Input/Output Organisation of Computer Architecture
Answer» The correct ANSWER is (d) CRC Best explanation: The last 5 bits of the PACKET is used for error CHECKING, that is cyclic REDUNDANCY check.

Discussion

37.	Single ended transmission means _________(a) That all the signals have a similar bit pattern(b) That the signals have a common source(c) That the signals have a common ground return(d) That the signals have a similar voltage signatureThis question was addressed to me in an interview.My enquiry is from SCSI BUS-2 topic in portion Input/Output Organisation of Computer Architecture
Answer» CORRECT answer is (C) That the signals have a common GROUND return Easy EXPLANATION: These type of signals are a common feature of the SCSI BUS.

Discussion

38.	ANSI stands for _________(a) American National System Interface(b) ASCII National Standard Interface(c) American Network System Interface(d) American National Standard InstituteI have been asked this question in final exam.My question is based upon SCSI BUS-2 topic in portion Input/Output Organisation of Computer Architecture
Answer» CORRECT choice is (d) AMERICAN National STANDARD Institute For EXPLANATION: This a standard for DESIGNING BUSes and other system components.

Discussion

39.	The device connected to the BUS are given addresses of ____ bit.(a) 24(b) 64(c) 32(d) 16The question was asked during an interview for a job.My doubt is from PCI BUS-2 in chapter Input/Output Organisation of Computer Architecture
Answer» Right choice is (B) 64 For EXPLANATION I would SAY: Each of the devices connected to the BUS will be allocated an address during the INITIALIZATION phase.

Discussion

40.	PCI stands for _______(a) Peripheral Component Interconnect(b) Peripheral Computer Internet(c) Processor Computer Interconnect(d) Processor Cable InterconnectI had been asked this question in homework.Question is taken from PCI BUS-1 in division Input/Output Organisation of Computer Architecture
Answer» Correct answer is (a) Peripheral COMPONENT Interconnect Best EXPLANATION: The PCI BUS is used as an EXTENSION for the processor BUS.

Discussion

41.	The key feature of the PCI BUS is _________(a) Low cost connectivity(b) Plug and Play capability(c) Expansion of Bandwidth(d) None of the mentionedThis question was posed to me in my homework.This intriguing question originated from PCI BUS-1 topic in portion Input/Output Organisation of Computer Architecture
Answer» Right answer is (b) Plug and PLAY capability Easy explanation: The PCI BUS was the first to introduce plug and play INTERFACE for I/O DEVICES.

Discussion

42.	The double buffer is used for _________(a) Enabling retrieval of multiple bits of input(b) Combining the input and output operations(c) Extending the buffer capacity(d) None of the mentionedI have been asked this question in an interview for job.I need to ask this question from Serial Port topic in portion Input/Output Organisation of Computer Architecture
Answer» The correct OPTION is (a) Enabling RETRIEVAL of multiple BITS of input The BEST I can explain: None.

Discussion

43.	To overcome multiple signals being generated upon a single press of the button, we make use of ______(a) Generator circuit(b) Debouncing circuit(c) Multiplexer(d) XOR circuitI had been asked this question in a job interview.My question is taken from Parallel Port in section Input/Output Organisation of Computer Architecture
Answer» The correct CHOICE is (b) Debouncing circuit The best I can explain: When the button is pressed, the contact SURFACES bounce and hence it might lead to the generation of multiple SIGNALS. In ORDER to overcome this, we use Debouncing circuits.

Discussion

44.	________ is an extension of the processor BUS.(a) SCSI BUS(b) USB(c) PCI BUS(d) None of the mentionedThe question was posed to me in semester exam.I would like to ask this question from Standard I/O Interfaces in division Input/Output Organisation of Computer Architecture
Answer» RIGHT option is (c) PCI BUS Easy explanation: The PCI BUS is used as an EXTENSION of the processor BUS and DEVICES CONNECTED to it, is like connected to the Processor itself.

Discussion

45.	User programmable terminals that combine VDT hardware with built-in microprocessor is _____(a) KIPs(b) Pc(c) Mainframe(d) Intelligent terminalsI got this question in a national level competition.I need to ask this question from Interface Circuits in division Input/Output Organisation of Computer Architecture
Answer» RIGHT ANSWER is (d) INTELLIGENT terminals Explanation: NONE.

Discussion

46.	The two facilities provided by the debugger is __________(a) Trace points(b) Break points(c) Compile(d) Both Trace and Break pointsThe question was asked in exam.My question is from Exceptions topic in division Input/Output Organisation of Computer Architecture
Answer» The CORRECT option is (d) Both TRACE and Break points Best explanation: The debugger provides us with the TWO facilities to improve the checking of ERRORS.

Discussion

47.	In daisy chaining device 0 will pass the signal only if it has _______(a) Interrupt request(b) No interrupt request(c) Both No interrupt and Interrupt request(d) None of the mentionedThis question was addressed to me in homework.This intriguing question originated from Interrupts in section Input/Output Organisation of Computer Architecture
Answer» The correct OPTION is (b) No INTERRUPT request To elaborate: In DAISY chaining since there is only one request line and only one acknowledges line, the acknowledge signal passes from DEVICE to device until the one with the interrupt is found.

Discussion

48.	Which interrupt is unmaskable?(a) RST 5.5(b) RST 7.5(c) TRAP(d) Both RST 5.5 and 7.5I got this question in quiz.I need to ask this question from Interrupts topic in portion Input/Output Organisation of Computer Architecture
Answer» Correct option is (C) TRAP The BEST I can explain: The trap is a non-maskable interrupt as it deals with the ongoing process in the processor. The trap is initiated by the process being executed due to lack of data required for its completion. HENCE trap is unmaskable.

Discussion

49.	The most important objective of the USB is to provide ______(a) Isochronous transmission(b) Plug and play(c) Easy device connection(d) All of the mentionedThis question was posed to me by my school teacher while I was bunking the class.The doubt is from USB in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT ANSWER is (d) All of the mentioned The best I can explain: The above are all the COMMON FEATURES of the USB.

Discussion

50.	The USB address space can be shared by the user’s memory space.(a) True(b) FalseThis question was posed to me in examination.The query is from USB in chapter Input/Output Organisation of Computer Architecture
Answer» The correct option is (b) False To explain: The USB memory SPACE is not under any ADDRESS spaces and cannot be accessed.

Discussion

Explore topic-wise InterviewSolutions in .

The BSY signal signifies _________(a) The BUs is busy(b) The controller is busy(c) The Initiator is busy(d) The Target is BusyI got this question during an interview for a job.I'd like to ask this question from SCSI BUS-1 topic in portion Input/Output Organisation of Computer Architecture

In a data transfer operation involving SCSI BUS, the control is with ______(a) Initiator(b) Target(c) SCSI controller(d) Target ControllerThe question was posed to me in semester exam.My doubt is from SCSI BUS-1 topic in chapter Input/Output Organisation of Computer Architecture

The signal used to initiate device select ________(a) IRDY#(b) S/BE(c) DEVSEL#(d) IDSEL#This question was addressed to me by my college director while I was bunking the class.I'm obligated to ask this question of PCI BUS-2 topic in chapter Input/Output Organisation of Computer Architecture

The PCI BUS has _____ interrupt request lines.(a) 6(b) 1(c) 4(d) 3This question was addressed to me in an interview for internship.The doubt is from PCI BUS-2 in portion Input/Output Organisation of Computer Architecture

Interrupts form an important part of _____ systems.(a) Batch processing(b) Multitasking(c) Real-time processing(d) Multi-userThe question was asked in exam.This question is from Interrupts in chapter Input/Output Organisation of Computer Architecture

The interrupt-request line is a part of the ___________(a) Data line(b) Control line(c) Address line(d) None of the mentionedI got this question during an interview.My question is from Interrupts in division Input/Output Organisation of Computer Architecture

The data packets can contain data upto ______(a) 512 bytes(b) 256 bytes(c) 1024 bytes(d) 2 KBThis question was posed to me during a job interview.I want to ask this question from USB in division Input/Output Organisation of Computer Architecture

The PCI BUS supports _____ address space/s.(a) I/O(b) Memory(c) Configuration(d) All of the mentionedThis question was posed to me at a job interview.My question comes from PCI BUS-1 in section Input/Output Organisation of Computer Architecture

The PCI follows a set of standards primarily used in _____ PC’s.(a) Intel(b) Motorola(c) IBM(d) SUNThe question was asked in unit test.My question is taken from PCI BUS-1 topic in division Input/Output Organisation of Computer Architecture

The Status flag circuit is implemented using _____(a) RS flip flop(b) D flip flop(c) JK flip flop(d) Xor circuitThis question was addressed to me in semester exam.This is a very interesting question from Parallel Port topic in chapter Input/Output Organisation of Computer Architecture

Which is fed into the BUS first by the initiator?(a) Data(b) Address(c) Commands or controls(d) Address, Commands or controlsThis question was addressed to me in exam.The question is from Synchronous BUS topic in division Input/Output Organisation of Computer Architecture

The device which starts data transfer is called __________(a) Master(b) Transactor(c) Distributor(d) InitiatorThis question was addressed to me in an interview for job.This question is from Synchronous BUS topic in section Input/Output Organisation of Computer Architecture

The circuit used for the request line is a _________(a) Open-collector(b) EX-OR circuit(c) Open-drain(d) Nand circuitThis question was addressed to me in my homework.The origin of the question is Bus Arbitration in section Input/Output Organisation of Computer Architecture

The registers of the controller are ______(a) 64 bits(b) 24 bits(c) 32 bits(d) 16 bitsI had been asked this question in an international level competition.This question is from Direct Memory Access topic in division Input/Output Organisation of Computer Architecture

The 4 bit PID’s are transmitted twice.(a) True(b) FalseThis question was addressed to me in my homework.I want to ask this question from USB in portion Input/Output Organisation of Computer Architecture

The high speed mode of operation of the USB was introduced by _____(a) ISA(b) USB 3.0(c) USB 2.0(d) ANSIThis question was addressed to me in an international level competition.The doubt is from USB topic in chapter Input/Output Organisation of Computer Architecture

The transfer rate, when the USB is operating in low-speed of operation is _____(a) 5 Mb/s(b) 12 Mb/s(c) 2.5 Mb/s(d) 1.5 Mb/sThis question was posed to me in final exam.This intriguing question originated from USB in portion Input/Output Organisation of Computer Architecture

______ is used as an intermediate to extend the processor BUS.(a) Bridge(b) Router(c) Connector(d) GatewayThis question was addressed to me in semester exam.I need to ask this question from Standard I/O Interfaces topic in section Input/Output Organisation of Computer Architecture

The DMA transfers are performed by a control circuit called as __________(a) Device interface(b) DMA controller(c) Data controller(d) OverlookerThe question was asked in semester exam.My query is from Direct Memory Access in division Input/Output Organisation of Computer Architecture

The program used to find out errors is called __________(a) Debugger(b) Compiler(c) Assembler(d) ScannerI had been asked this question by my school teacher while I was bunking the class.The query is from Exceptions in section Input/Output Organisation of Computer Architecture

The last field in the packet is ______(a) PID(b) ADDR(c) ENDP(d) CRCI have been asked this question during a job interview.This intriguing question comes from USB topic in section Input/Output Organisation of Computer Architecture

The device connected to the BUS are given addresses of ____ bit.(a) 24(b) 64(c) 32(d) 16The question was asked during an interview for a job.My doubt is from PCI BUS-2 in chapter Input/Output Organisation of Computer Architecture

PCI stands for _______(a) Peripheral Component Interconnect(b) Peripheral Computer Internet(c) Processor Computer Interconnect(d) Processor Cable InterconnectI had been asked this question in homework.Question is taken from PCI BUS-1 in division Input/Output Organisation of Computer Architecture

________ is an extension of the processor BUS.(a) SCSI BUS(b) USB(c) PCI BUS(d) None of the mentionedThe question was posed to me in semester exam.I would like to ask this question from Standard I/O Interfaces in division Input/Output Organisation of Computer Architecture

The two facilities provided by the debugger is __________(a) Trace points(b) Break points(c) Compile(d) Both Trace and Break pointsThe question was asked in exam.My question is from Exceptions topic in division Input/Output Organisation of Computer Architecture

Which interrupt is unmaskable?(a) RST 5.5(b) RST 7.5(c) TRAP(d) Both RST 5.5 and 7.5I got this question in quiz.I need to ask this question from Interrupts topic in portion Input/Output Organisation of Computer Architecture

The USB address space can be shared by the user’s memory space.(a) True(b) FalseThis question was posed to me in examination.The query is from USB in chapter Input/Output Organisation of Computer Architecture