181 + Interview Questions in Input Output Organisation in Computer Architecture Page 2 InterviewSolution

51.	UART stands for ________(a) Universal Asynchronous Relay Transmission(b) Universal Accumulator Register Transfer(c) Universal Asynchronous Receiver Transmitter(d) None of the mentionedI have been asked this question in an internship interview.I'd like to ask this question from Serial Port topic in division Input/Output Organisation of Computer Architecture
Answer» The correct answer is (c) Universal Asynchronous Receiver Transmitter Best explanation: The UART is a STANDARD DEVELOPED for DESIGNING serial PORTS.

Discussion

52.	The mode of transmission of data, where one bit is sent for each clock cycle is ______(a) Asynchronous(b) Parallel(c) Serial(d) IsochronousI had been asked this question by my school teacher while I was bunking the class.This interesting question is from Serial Port topic in section Input/Output Organisation of Computer Architecture
Answer» The CORRECT CHOICE is (d) Isochronous Easiest EXPLANATION: In the isochronous mode of transmission, each bit of the data is sent per each CYCLE.

Discussion

53.	In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.(a) Valid bit(b) Idle bit(c) Interrupt enable bit(d) Status or data registerThe question was asked during an interview.I'm obligated to ask this question of Parallel Port in division Input/Output Organisation of Computer Architecture
Answer» CORRECT ANSWER is (d) Status or DATA register To EXPLAIN: NONE.

Discussion

54.	The disadvantage of using a parallel mode of communication is ______(a) It is costly(b) Leads to erroneous data transfer(c) Security of data(d) All of the mentionedThis question was posed to me in an interview for job.The above asked question is from Parallel Port topic in division Input/Output Organisation of Computer Architecture
Answer» Right answer is (a) It is costly Easiest EXPLANATION: The parallel MODE of data transfer is costly as it INVOLVES data being SENT over parallel lines.

Discussion

55.	What is the interface circuit?(a) Helps in installing of the software driver for the device(b) Houses the buffer that helps in data transfer(c) Helps in the decoding of the address on the address BUs(d) None of the mentionedThis question was addressed to me in class test.My question is taken from Interface Circuits in division Input/Output Organisation of Computer Architecture
Answer» The CORRECT answer is (c) Helps in the decoding of the address on the address BUS To elaborate: Once the address is put on the BUS the interface circuit decodes the address and USES the buffer SPACE to transfer data.

Discussion

56.	The meter in and out lines are used for __________(a) Monitoring the usage of devices(b) Monitoring the amount of data transferred(c) Measure the CPU usage(d) None of the mentionedI have been asked this question during a job interview.This key question is from Asynchronous BUS in division Input/Output Organisation of Computer Architecture
Answer» Right answer is (a) MONITORING the usage of devices Best explanation: The LINE is used to MONITOR the usage of the device for a process.

Discussion

57.	The master indicates that the address is loaded onto the BUS, by activating _____ signal.(a) MSYN(b) SSYN(c) WMFC(d) INTRThis question was addressed to me in an interview.Question is taken from Asynchronous BUS topic in division Input/Output Organisation of Computer Architecture
Answer» The CORRECT choice is (a) MSYN Best explanation: The signal activated by the master in the ASYNCHRONOUS MODE of transmission is used to INTIMATE the slave the required data is on the BUS.

Discussion

58.	The delays caused in the switching of the timing signals is due to __________(a) Memory access time(b) WMFC(c) Propagation delay(d) Processor delayThe question was asked in final exam.Query is from Synchronous BUS in chapter Input/Output Organisation of Computer Architecture
Answer» The CORRECT choice is (c) Propagation delay The best EXPLANATION: The time TAKEN for the signal to REACH the BUS from the device or the circuit accounts for this delay.

Discussion

59.	The classification of BUSes into synchronous and asynchronous is based on __________(a) The devices connected to them(b) The type of data transfer(c) The Timing of data transfers(d) None of the mentionedI have been asked this question in unit test.My query is from Synchronous BUS topic in chapter Input/Output Organisation of Computer Architecture
Answer» CORRECT option is (c) The TIMING of data transfers For explanation I would SAY: The BUS is classified into different types for the convenience of use and depending on the DEVICE.

Discussion

60.	When dealing with multiple devices interrupts, which mechanism is easy to implement?(a) Polling method(b) Vectored interrupts(c) Interrupt nesting(d) None of the mentionedThis question was addressed to me in exam.Asked question is from Interrupts topic in division Input/Output Organisation of Computer Architecture
Answer» Correct answer is (a) Polling method Easy explanation: In this method, the PROCESSOR checks the IRQ bits of all the devices, WHICHEVER is ENABLED first that DEVICE is serviced.

Discussion

61.	The starting address sent by the device in vectored interrupt is called as __________(a) Location id(b) Interrupt vector(c) Service location(d) Service idI got this question in class test.My question comes from Interrupts topic in chapter Input/Output Organisation of Computer Architecture
Answer» RIGHT CHOICE is (B) INTERRUPT vector Explanation: NONE.

Discussion

62.	When the process requests for a DMA transfer?(a) Then the process is temporarily suspended(b) The process continues execution(c) Another process gets executed(d) process is temporarily suspended & Another process gets executedI got this question in an online interview.Asked question is from Direct Memory Access topic in chapter Input/Output Organisation of Computer Architecture
Answer» Correct choice is (d) process is temporarily suspended & Another process gets executed To explain I would say: The process REQUESTING the TRANSFER is paused and the operation is performed, MEANWHILE another process is RUN on the processor.

Discussion

63.	What are the different modes of operation of a computer?(a) User and System mode(b) User and Supervisor mode(c) Supervisor and Trace mode(d) Supervisor, User and Trace modeThis question was posed to me in a national level competition.This question is from Exceptions topic in portion Input/Output Organisation of Computer Architecture
Answer» Correct ANSWER is (b) User and Supervisor MODE Easy EXPLANATION: The user PROGRAMS are in the user mode and the system crucial programs are in the supervisor mode.

Discussion

64.	The system is notified of a read or write operation by ___________(a) Appending an extra bit of the address(b) Enabling the read or write bits of the devices(c) Raising an appropriate interrupt signal(d) Sending a special signal along the BUSI got this question in class test.This intriguing question comes from Accessing I/O Devices in portion Input/Output Organisation of Computer Architecture
Answer» Correct option is (d) Sending a special signal ALONG the BUS Easy explanation: It is necessary for the PROCESSOR to send a signal intimating the REQUEST as either READ or write.

Discussion

65.	In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.(a) False(b) TrueI had been asked this question during an interview.My question comes from Accessing I/O Devices in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT answer is (B) True Easy EXPLANATION: This type of access is called as I/O MAPPED DEVICES.

Discussion

66.	HVD stands for _________(a) High Voltage Differential(b) High Voltage Density(c) High Video Definition(d) None of the mentionedI had been asked this question in homework.Query is from SCSI BUS-2 in division Input/Output Organisation of Computer Architecture
Answer» Correct answer is (a) HIGH VOLTAGE Differential To EXPLAIN I would say: This is a type of SIGNALING which uses 5v of current.

Discussion

67.	The ______ is the BUS used in Macintosh PC’s.(a) NuBUS(b) EISA(c) PCI(d) None of the mentionedThis question was addressed to me during an interview.I'm obligated to ask this question of PCI BUS-1 in portion Input/Output Organisation of Computer Architecture
Answer» The correct ANSWER is (a) NUBUS For explanation I would SAY: The NuBUS is an extension of the PROCESSOR BUS in Macintosh PC’s.

Discussion

68.	The transformation between the Parallel and serial ports is done with the help of ______(a) Flip flops(b) Logic circuits(c) Shift registers(d) None of the mentionedThe question was asked in exam.Asked question is from Serial Port topic in portion Input/Output Organisation of Computer Architecture
Answer» The correct option is (C) Shift REGISTERS Easiest explanation: The Shift registers are used to output the DATA in the desired format BASED on the need.

Discussion

69.	The primary function of the BUS is __________(a) To connect the various devices to the cpu(b) To provide a path for communication between the processor and other devices(c) To facilitate data transfer between various devices(d) All of the mentionedI have been asked this question in an interview.The question is from Synchronous BUS topic in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT choice is (a) To CONNECT the various devices to the cpu To elaborate: The BUS is USED to allow the PASSAGE of commands and data between cpu and devices.

Discussion

70.	To overcome the lag in the operating speeds of the I/O device and the processor we use ___________(a) BUffer spaces(b) Status flags(c) Interrupt signals(d) ExceptionsThe question was posed to me in final exam.Question is from Accessing I/O Devices topic in division Input/Output Organisation of Computer Architecture
Answer» Right option is (b) STATUS flags To ELABORATE: The processor OPERATING is much faster than that of the I/O devices, so by USING the status flags the processor need not wait till the I/O operation is done. It can continue with its work until the status FLAG is set.

Discussion

71.	______ BUS arbitration approach uses the involvement of the processor.(a) Centralised arbitration(b) Distributed arbitration(c) Random arbitration(d) All of the mentionedThe question was asked during an internship interview.Question is taken from Bus Arbitration in chapter Input/Output Organisation of Computer Architecture
Answer» The CORRECT option is (a) Centralised arbitration Explanation: In this APPROACH, the PROCESSOR takes into account the various parameters and assigns the BUS to that DEVICE.

Discussion

72.	The SOF is transmitted every ______(a) 1s(b) 5s(c) 1ms(d) 1UsThe question was asked in semester exam.This intriguing question comes from USB in portion Input/Output Organisation of Computer Architecture
Answer» RIGHT OPTION is (C) 1ms Explanation: NONE.

Discussion

73.	A narrow SCSI BUS has _____ data lines.(a) 6(b) 8(c) 16(d) 4The question was posed to me during an interview for a job.This is a very interesting question from SCSI BUS-2 in chapter Input/Output Organisation of Computer Architecture
Answer» The correct choice is (b) 8 The explanation: The SCSI BUS which is NARROW is CAPABLE of transferring 8 BITS of data at a time.

Discussion

74.	USB is a parallel mode of transmission of data and this enables for the fast speeds of data transfers.(a) True(b) FalseI got this question in a national level competition.My doubt is from USB topic in section Input/Output Organisation of Computer Architecture
Answer» Correct ANSWER is (b) False Easiest EXPLANATION: The USB does a serial MODE of DATA TRANSFER.

Discussion

75.	The controller uses _____ to help with the transfers when handling network interfaces.(a) Input Buffer storage(b) Signal enhancers(c) Bridge circuits(d) All of the mentionedI had been asked this question in class test.I would like to ask this question from Direct Memory Access topic in division Input/Output Organisation of Computer Architecture
Answer» RIGHT CHOICE is (a) Input BUFFER storage Easy explanation: The controller stores the data to transfer in the buffer and then transfers it.

Discussion

76.	The master is also called as _____ in PCI terminology.(a) Initiator(b) Commander(c) Chief(d) StarterThis question was addressed to me during an online interview.This question is from PCI BUS-1 topic in portion Input/Output Organisation of Computer Architecture
Answer» CORRECT ANSWER is (a) Initiator To explain: The MASTER is also called as an initiator in PCI TERMINOLOGY as it is the one that initiates a data TRANSFER.

Discussion

77.	The output of the encoder circuit is/are ______(a) ASCII code(b) ASCII code and the valid signal(c) Encoded signal(d) None of the mentionedI have been asked this question in an online quiz.I'd like to ask this question from Parallel Port topic in division Input/Output Organisation of Computer Architecture
Answer» Right answer is (b) ASCII CODE and the valid SIGNAL The BEST EXPLANATION: The encoder outputs the ASCII value along with the valid signal which indicates that a key was pressed.

Discussion

78.	The controller is connected to the ____(a) Processor BUS(b) System BUS(c) External BUS(d) None of the mentionedI have been asked this question during a job interview.Query is from Direct Memory Access in section Input/Output Organisation of Computer Architecture
Answer» The CORRECT choice is (b) System BUS The BEST EXPLANATION: The controller is directly connected to the system BUS to PROVIDE faster transfer of data.

Discussion

79.	The code sent by the device in vectored interrupt is _____ long.(a) upto 16 bits(b) upto 32 bits(c) upto 24 bits(d) 4-8 bitsI have been asked this question during a job interview.This key question is from Interrupts topic in chapter Input/Output Organisation of Computer Architecture
Answer» RIGHT OPTION is (d) 4-8 bits The BEST EXPLANATION: NONE.

Discussion

80.	The device can send a message to the host by taking part in _____ for the communication path.(a) Arbitration(b) Polling(c) Prioritizing(d) None of the mentionedThe question was asked during a job interview.Question is from USB in division Input/Output Organisation of Computer Architecture
Answer» CORRECT OPTION is (B) Polling The EXPLANATION: NONE.

Discussion

81.	The SCSI BUS is connected to the processor through _____(a) SCSI Controller(b) Bridge(c) Switch(d) None of the mentionedThe question was asked during an interview.I need to ask this question from SCSI BUS-2 in division Input/Output Organisation of Computer Architecture
Answer» CORRECT answer is (a) SCSI Controller For explanation: This is used to COORDINATE and MONITOR the data TRANSFER over the BUS.

Discussion

82.	In the output interface of the parallel port, along with the valid signal ______ is also sent.(a) Data(b) Idle signal(c) Interrupt(d) Acknowledge signalThis question was addressed to me at a job interview.This intriguing question comes from Parallel Port topic in chapter Input/Output Organisation of Computer Architecture
Answer» The CORRECT answer is (b) Idle SIGNAL Easiest explanation: The idle signal is used to check if the device is idle and ready to RECEIVE data.

Discussion

83.	The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is _____(a) BUS side(b) Port side(c) Hardwell side(d) Software sideThe question was posed to me in unit test.This question is from Interface Circuits in division Input/Output Organisation of Computer Architecture
Answer» The correct OPTION is (B) PORT SIDE Easy explanation: This side connects the device to the MOTHERBOARD.

Discussion

84.	The transmission on the asynchronous BUS is also called _____(a) Switch mode transmission(b) Variable transfer(c) Bulk transfer(d) Hand-Shake transmissionThis question was addressed to me by my college professor while I was bunking the class.I want to ask this question from Asynchronous BUS in section Input/Output Organisation of Computer Architecture
Answer» RIGHT choice is (d) Hand-Shake transmission The best I can EXPLAIN: The ASYNCHRONOUS transmission is termed as Hand-Shake transfer because the MASTER intimates the slave after each STEP of the transfer.

Discussion

85.	In IBM’s S360/370 systems _____ lines are used to select the I/O devices.(a) SCAN in and out(b) Connect(c) Search(d) PeripheralI had been asked this question in an interview.My question is from Asynchronous BUS topic in chapter Input/Output Organisation of Computer Architecture
Answer» RIGHT option is (a) SCAN in and out The explanation is: The signal is USED to scan and connect to input or OUTPUT DEVICES.

Discussion

86.	The devices with variable speeds are usually connected using asynchronous BUS.(a) True(b) FalseThis question was addressed to me in an international level competition.My question is based upon Asynchronous BUS in portion Input/Output Organisation of Computer Architecture
Answer» The correct option is (a) True For EXPLANATION: The DEVICES with variable SPEEDS are connected USING asynchronous BUS, as the devices SHARE a master-slave relationship.

Discussion

87.	The time for which the data is to be on the BUS is affected by __________(a) Propagation delay of the circuit(b) Setup time of the device(c) Memory access time(d) Propagation delay of the circuit & Setup time of the deviceThe question was posed to me in an interview for internship.This interesting question is from Synchronous BUS in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT OPTION is (d) Propagation delay of the circuit & SETUP time of the device For explanation: The time for which the data is held is LARGER than the time taken for propagation delay and setup time.

Discussion

88.	How is a device selected in Distributed arbitration?(a) By NANDing the signals passed on all the 4 lines(b) By ANDing the signals passed on all the 4 lines(c) By ORing the signals passed on all the 4 lines(d) None of the mentionedThe question was asked in final exam.My enquiry is from Bus Arbitration topic in portion Input/Output Organisation of Computer Architecture
Answer» The correct CHOICE is (c) By ORing the SIGNALS passed on all the 4 lines Easy explanation: The OR output of all the 4 lines is OBTAINED and the DEVICE with the LARGER value is assigned the BUS.

Discussion

89.	The device which is allowed to initiate data transfers on the BUS at any time is called _____(a) BUS master(b) Processor(c) BUS arbitrator(d) ControllerI have been asked this question during an interview.This interesting question is from Bus Arbitration topic in chapter Input/Output Organisation of Computer Architecture
Answer» RIGHT CHOICE is (a) BUS MASTER Best explanation: The DEVICE which is currently accessing the BUS is CALLED as the BUS master.

Discussion

90.	The DMA controller has _______ registers.(a) 4(b) 2(c) 3(d) 1The question was posed to me in semester exam.Question is from Direct Memory Access topic in section Input/Output Organisation of Computer Architecture
Answer» Correct answer is (c) 3 The best explanation: The CONTROLLER USES the registers to STORE the starting address, word count and the status of the OPERATION.

Discussion

91.	_____ is/are types of exceptions.(a) Trap(b) Interrupt(c) System calls(d) All of the mentionedThe question was asked by my school principal while I was bunking the class.My query is from Exceptions in portion Input/Output Organisation of Computer Architecture
Answer» The correct CHOICE is (d) All of the mentioned To EXPLAIN I would SAY: None.

Discussion

92.	An interrupt that can be temporarily ignored is ___________(a) Vectored interrupt(b) Non-maskable interrupt(c) Maskable interrupt(d) High priority interruptI got this question during an interview for a job.I'm obligated to ask this question of Interrupts in division Input/Output Organisation of Computer Architecture
Answer» Right CHOICE is (C) Maskable interrupt The EXPLANATION: The maskable interrupts are usually LOW priority interrupts which can be ignored if a higher priority PROCESS is being executed.

Discussion

93.	_________ method is used to establish priority by serially connecting all devices that request an interrupt.(a) Vectored-interrupting(b) Daisy chain(c) Priority(d) PollingI had been asked this question during an interview.I want to ask this question from Interrupts topic in division Input/Output Organisation of Computer Architecture
Answer» RIGHT CHOICE is (b) Daisy chain Explanation: In the Daisy chain mechanism, all the devices are connected using a single request line and they’re serviced based on the interrupting DEVICE’s priority.

Discussion

94.	The initial address of a device just connected to the HUB is ________(a) AHFG890(b) 0000000(c) FFFFFFF(d) 0101010The question was posed to me during a job interview.My question comes from USB in portion Input/Output Organisation of Computer Architecture
Answer» Right answer is (B) 0000000 Explanation: By standard, the usual ADDRESS of a NEW device is zero.

Discussion

95.	The I/O devices form the _____ of the tree structure.(a) Leaves(b) Subordinate roots(c) Left subtrees(d) Right subtreesThis question was addressed to me in exam.Origin of the question is USB in chapter Input/Output Organisation of Computer Architecture
Answer» RIGHT answer is (a) LEAVES The best EXPLANATION: The I/o DEVICES form the leaves of the structure.

Discussion

96.	In SCSI transfers the processor is not aware of the data being transferred.(a) True(b) FalseThe question was posed to me in class test.This key question is from SCSI BUS-1 topic in section Input/Output Organisation of Computer Architecture
Answer» The CORRECT option is (a) True Easy explanation: The processor or the controller is unaware of the DATA being TRANSFERRED.

Discussion

97.	The signal used to indicate that the slave is ready is _____(a) SLRY#(b) TRDY#(c) DSDY#(d) None of the mentionedI got this question in unit test.The origin of the question is PCI BUS-2 in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT choice is (B) TRDY# The explanation is: None.

Discussion

98.	The conversion from parallel to serial data transmission and vice versa takes place inside the interface circuits.(a) True(b) FalseI have been asked this question by my school principal while I was bunking the class.Question is taken from Interface Circuits in chapter Input/Output Organisation of Computer Architecture
Answer» Correct choice is (a) True Best explanation: By doing this the interface CIRCUITS PROVIDE a better interconnection between DEVICES.

Discussion

99.	ISO stands for __________(a) International Standards Organisation(b) International Software Organisation(c) Industrial Standards Organisation(d) Industrial Software OrganisationThis question was addressed to me by my college professor while I was bunking the class.This intriguing question originated from Standard I/O Interfaces topic in portion Input/Output Organisation of Computer Architecture
Answer» CORRECT CHOICE is (a) International STANDARDS Organisation Explanation: The ISO is yet another architectural standard, used to DESIGN systems.

Discussion

100.	MRDC stands for _______(a) Memory Read Enable(b) Memory Ready Command(c) Memory Re-direct Command(d) None of the mentionedI had been asked this question during an online interview.This is a very interesting question from Asynchronous BUS topic in portion Input/Output Organisation of Computer Architecture
Answer» The correct option is (B) Memory READY Command Explanation: The command is used to initiate a read from memory OPERATION.

Discussion

Explore topic-wise InterviewSolutions in .

The master indicates that the address is loaded onto the BUS, by activating _____ signal.(a) MSYN(b) SSYN(c) WMFC(d) INTRThis question was addressed to me in an interview.Question is taken from Asynchronous BUS topic in division Input/Output Organisation of Computer Architecture

The delays caused in the switching of the timing signals is due to __________(a) Memory access time(b) WMFC(c) Propagation delay(d) Processor delayThe question was asked in final exam.Query is from Synchronous BUS in chapter Input/Output Organisation of Computer Architecture

The starting address sent by the device in vectored interrupt is called as __________(a) Location id(b) Interrupt vector(c) Service location(d) Service idI got this question in class test.My question comes from Interrupts topic in chapter Input/Output Organisation of Computer Architecture

In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.(a) False(b) TrueI had been asked this question during an interview.My question comes from Accessing I/O Devices in portion Input/Output Organisation of Computer Architecture

HVD stands for _________(a) High Voltage Differential(b) High Voltage Density(c) High Video Definition(d) None of the mentionedI had been asked this question in homework.Query is from SCSI BUS-2 in division Input/Output Organisation of Computer Architecture

The ______ is the BUS used in Macintosh PC’s.(a) NuBUS(b) EISA(c) PCI(d) None of the mentionedThis question was addressed to me during an interview.I'm obligated to ask this question of PCI BUS-1 in portion Input/Output Organisation of Computer Architecture

The transformation between the Parallel and serial ports is done with the help of ______(a) Flip flops(b) Logic circuits(c) Shift registers(d) None of the mentionedThe question was asked in exam.Asked question is from Serial Port topic in portion Input/Output Organisation of Computer Architecture

The SOF is transmitted every ______(a) 1s(b) 5s(c) 1ms(d) 1UsThe question was asked in semester exam.This intriguing question comes from USB in portion Input/Output Organisation of Computer Architecture

A narrow SCSI BUS has _____ data lines.(a) 6(b) 8(c) 16(d) 4The question was posed to me during an interview for a job.This is a very interesting question from SCSI BUS-2 in chapter Input/Output Organisation of Computer Architecture

USB is a parallel mode of transmission of data and this enables for the fast speeds of data transfers.(a) True(b) FalseI got this question in a national level competition.My doubt is from USB topic in section Input/Output Organisation of Computer Architecture

The master is also called as _____ in PCI terminology.(a) Initiator(b) Commander(c) Chief(d) StarterThis question was addressed to me during an online interview.This question is from PCI BUS-1 topic in portion Input/Output Organisation of Computer Architecture

The controller is connected to the ____(a) Processor BUS(b) System BUS(c) External BUS(d) None of the mentionedI have been asked this question during a job interview.Query is from Direct Memory Access in section Input/Output Organisation of Computer Architecture

The code sent by the device in vectored interrupt is _____ long.(a) upto 16 bits(b) upto 32 bits(c) upto 24 bits(d) 4-8 bitsI have been asked this question during a job interview.This key question is from Interrupts topic in chapter Input/Output Organisation of Computer Architecture

The device can send a message to the host by taking part in _____ for the communication path.(a) Arbitration(b) Polling(c) Prioritizing(d) None of the mentionedThe question was asked during a job interview.Question is from USB in division Input/Output Organisation of Computer Architecture

The SCSI BUS is connected to the processor through _____(a) SCSI Controller(b) Bridge(c) Switch(d) None of the mentionedThe question was asked during an interview.I need to ask this question from SCSI BUS-2 in division Input/Output Organisation of Computer Architecture

In IBM’s S360/370 systems _____ lines are used to select the I/O devices.(a) SCAN in and out(b) Connect(c) Search(d) PeripheralI had been asked this question in an interview.My question is from Asynchronous BUS topic in chapter Input/Output Organisation of Computer Architecture

The devices with variable speeds are usually connected using asynchronous BUS.(a) True(b) FalseThis question was addressed to me in an international level competition.My question is based upon Asynchronous BUS in portion Input/Output Organisation of Computer Architecture

The DMA controller has _______ registers.(a) 4(b) 2(c) 3(d) 1The question was posed to me in semester exam.Question is from Direct Memory Access topic in section Input/Output Organisation of Computer Architecture

_____ is/are types of exceptions.(a) Trap(b) Interrupt(c) System calls(d) All of the mentionedThe question was asked by my school principal while I was bunking the class.My query is from Exceptions in portion Input/Output Organisation of Computer Architecture

The initial address of a device just connected to the HUB is ________(a) AHFG890(b) 0000000(c) FFFFFFF(d) 0101010The question was posed to me during a job interview.My question comes from USB in portion Input/Output Organisation of Computer Architecture

The I/O devices form the _____ of the tree structure.(a) Leaves(b) Subordinate roots(c) Left subtrees(d) Right subtreesThis question was addressed to me in exam.Origin of the question is USB in chapter Input/Output Organisation of Computer Architecture

In SCSI transfers the processor is not aware of the data being transferred.(a) True(b) FalseThe question was posed to me in class test.This key question is from SCSI BUS-1 topic in section Input/Output Organisation of Computer Architecture

The signal used to indicate that the slave is ready is _____(a) SLRY#(b) TRDY#(c) DSDY#(d) None of the mentionedI got this question in unit test.The origin of the question is PCI BUS-2 in portion Input/Output Organisation of Computer Architecture