181 + Interview Questions in Input Output Organisation in Computer Architecture Page 3 InterviewSolution

101.	In synchronous BUS, the devices get the timing signals from __________(a) Timing generator in the device(b) A common clock line(c) Timing signals are not used at all(d) None of the mentionedThis question was addressed to me in an online interview.I'd like to ask this question from Synchronous BUS in division Input/Output Organisation of Computer Architecture
Answer» CORRECT answer is (b) A COMMON clock line Easy explanation: The DEVICES RECEIVE their TIMING signals from the clock line of the BUS.

Discussion

102.	The Master strobes the slave at the end of each clock cycle in Synchronous BUS.(a) True(b) FalseThe question was posed to me in an international level competition.The above asked question is from Synchronous BUS topic in chapter Input/Output Organisation of Computer Architecture
Answer» The CORRECT CHOICE is (a) True Explanation: NONE.

Discussion

103.	The BUS busy line is used __________(a) To indicate the processor is busy(b) To indicate that the BUS master is busy(c) To indicate the BUS is already allocated(d) None of the mentionedThis question was posed to me in a job interview.My doubt is from Bus Arbitration in section Input/Output Organisation of Computer Architecture
Answer» Right option is (C) To INDICATE the BUS is ALREADY allocated To EXPLAIN: NONE.

Discussion

104.	What is the operation in Breakpoint mode?(a) The program is interrupted after each detection(b) The program will not be stopped and the errors are sorted out after the complete program is scanned(c) There is no effect on the program, i.e the program is executed without rectification of errors(d) The program is halted only at specific pointsI have been asked this question in an online interview.This interesting question is from Exceptions topic in division Input/Output Organisation of Computer Architecture
Answer» Correct OPTION is (d) The program is HALTED only at specific points Easiest EXPLANATION: The Breakpoint mode of operation allows the program to be halted at only specific locations.

Discussion

105.	Which table handle stores the addresses of the interrupt handling sub-routines?(a) Interrupt-vector table(b) Vector table(c) Symbol link table(d) None of the mentionedI have been asked this question during an interview for a job.This key question is from Interrupts topic in portion Input/Output Organisation of Computer Architecture
Answer» CORRECT OPTION is (a) Interrupt-vector table The EXPLANATION is: NONE.

Discussion

106.	In memory-mapped I/O ____________(a) The I/O devices and the memory share the same address space(b) The I/O devices have a separate address space(c) The memory and I/O devices have an associated address space(d) A part of the memory is specifically set aside for the I/O operationThe question was posed to me during a job interview.My question is from Accessing I/O Devices in chapter Input/Output Organisation of Computer Architecture
Answer» Correct answer is (a) The I/O DEVICES and the memory SHARE the same address space The EXPLANATION: Its the different MODES of accessing the i/o devices.

Discussion

107.	The CRC bits are computed based on the values of the _____(a) PID(b) ADDR(c) ENDP(d) Both ADDR and ENDPI got this question in semester exam.Asked question is from USB in chapter Input/Output Organisation of Computer Architecture
Answer» Correct option is (d) Both ADDR and ENDP Explanation: The CRC bits are CALCULATED BASED on the VALUES of the ADDRESS and endp.

Discussion

108.	The devices connected to USB is assigned a ____ address.(a) 9 bit(b) 16 bit(c) 4 bit(d) 7 bitThis question was posed to me during an interview for a job.The question is from USB topic in section Input/Output Organisation of Computer Architecture
Answer» Correct answer is (d) 7 bit To EXPLAIN I WOULD say: To MAKE it easier for RECOGNITION the devices are given 7 bit addresses.

Discussion

109.	_____ is used to reset all the device controls to their startup state.(a) SRT(b) RST(c) ATN(d) None of the mentionedI got this question in an online interview.I want to ask this question from SCSI BUS-1 topic in chapter Input/Output Organisation of Computer Architecture
Answer» The CORRECT ANSWER is (B) RST Easy EXPLANATION: NONE.

Discussion

110.	IRDY# signal is used for _______(a) Selecting the interrupt line(b) Sending an interrupt(c) Saying that the initiator is ready(d) None of the mentionedThe question was asked during an interview for a job.This interesting question is from PCI BUS-2 topic in chapter Input/Output Organisation of Computer Architecture
Answer» Correct option is (c) Saying that the initiator is ready For explanation I would say: The initiator TRANSMITS this SIGNAL to TELL the TARGET that it is ready.

Discussion

111.	______ address space gives the PCI its plug and plays capability.(a) Configuration(b) I/O(c) Memory(d) All of the mentionedThis question was addressed to me in a job interview.This intriguing question originated from PCI BUS-1 in chapter Input/Output Organisation of Computer Architecture
Answer» Correct option is (a) Configuration Explanation: The configuration ADDRESS SPACE is used to STORE the DETAILS of the CONNECTED device.

Discussion

112.	The _____ circuit enables the generation of the ASCII code when the key is pressed.(a) Generator(b) Debouncing(c) Encoder(d) LoggerI have been asked this question in unit test.This key question is from Parallel Port in division Input/Output Organisation of Computer Architecture
Answer» Right answer is (c) Encoder Best explanation: The SIGNAL GENERATED UPON the pressing of a button is encoded by the encoder CIRCUIT into the corresponding ASCII value.

Discussion

113.	IDE disk is connected to the PCI BUS using ______ interface.(a) ISA(b) ISO(c) ANSI(d) IEEEThis question was addressed to me during an interview for a job.Question is from Standard I/O Interfaces in division Input/Output Organisation of Computer Architecture
Answer» The CORRECT CHOICE is (a) ISA The EXPLANATION: NONE.

Discussion

114.	The video devices are connected to ______ BUS.(a) PCI(b) USB(c) HDMI(d) SCSIThis question was posed to me during an interview.I would like to ask this question from Standard I/O Interfaces in division Input/Output Organisation of Computer Architecture
Answer» Correct ANSWER is (d) SCSI The best explanation: The SCSI BUS is used to connect the VIDEO DEVICES to a PROCESSOR by PROVIDING a parallel BUS.

Discussion

115.	The status flags required for data transfer is present in _____(a) Device(b) Device driver(c) Interface circuit(d) None of the mentionedThis question was addressed to me in an interview for internship.Origin of the question is Interface Circuits in division Input/Output Organisation of Computer Architecture
Answer» Correct choice is (c) INTERFACE CIRCUIT For EXPLANATION: The circuit holds the FLAGS which are required for data TRANSFERS.

Discussion

116.	The MSYN signal is initiated __________(a) Soon after the address and commands are loaded(b) Soon after the decoding of the address(c) After the slave gets the commands(d) None of the mentionedI had been asked this question in a job interview.This interesting question is from Asynchronous BUS topic in division Input/Output Organisation of Computer Architecture
Answer» The CORRECT CHOICE is (b) SOON after the DECODING of the address The explanation: This signal is activated by the master to tell the slave that the required COMMANDS are on the BUS.

Discussion

117.	If during the execution of an instruction an exception is raised then __________(a) The instruction is executed and the exception is handled(b) The instruction is halted and the exception is handled(c) The processor completes the execution and saves the data and then handle the exception(d) None of the mentionedI got this question by my school principal while I was bunking the class.Question is from Exceptions topic in chapter Input/Output Organisation of Computer Architecture
Answer» Right option is (b) The instruction is HALTED and the EXCEPTION is handled For EXPLANATION I would say: Since the INTERRUPT was raised during the execution of the instruction, the instruction cannot be executed and the exception is served immediately.

Discussion

118.	The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be serviced is ___________(a) Polling(b) Vectored interrupts(c) Interrupt nesting(d) Simultaneous requestingThe question was asked during a job interview.My enquiry is from Interrupts topic in division Input/Output Organisation of Computer Architecture
Answer» RIGHT ANSWER is (b) VECTORED interrupts The explanation is: None.

Discussion

119.	A single Interrupt line can be used to service n different devices.(a) True(b) FalseI got this question in an online quiz.My doubt stems from Interrupts topic in chapter Input/Output Organisation of Computer Architecture
Answer» The CORRECT CHOICE is (a) True Explanation: NONE.

Discussion

120.	The method which offers higher speeds of I/O transfers is ___________(a) Interrupts(b) Memory mapping(c) Program-controlled I/O(d) DMAThis question was addressed to me during an interview for a job.This key question is from Accessing I/O Devices in section Input/Output Organisation of Computer Architecture
Answer» Correct choice is (d) DMA The explanation is: In DMA the I/O devices are directly allowed to interact with the memory WITHOUT the INTERVENTION of the processor and the transfers TAKE place in the FORM of blocks increasing the speed of operation.

Discussion

121.	The advantage of I/O mapped devices to memory mapped is ___________(a) The former offers faster transfer of data(b) The devices connected using I/O mapping have a bigger buffer space(c) The devices have to deal with fewer address lines(d) No advantage as suchThe question was posed to me during an interview for a job.I need to ask this question from Accessing I/O Devices in portion Input/Output Organisation of Computer Architecture
Answer» Correct CHOICE is (C) The devices have to deal with fewer address lines The explanation is: Since the I/O mapped devices have a separate address SPACE the address lines are limited by the amount of the space ALLOCATED.

Discussion

122.	_____ provides a separate physical connection to the memory.(a) PCI BUS(b) PCI interface(c) PCI bridge(d) Switch circuitI had been asked this question during an interview.My enquiry is from PCI BUS-1 topic in portion Input/Output Organisation of Computer Architecture
Answer» Correct answer is (c) PCI BRIDGE To ELABORATE: The PCI bridge is a CIRCUIT that acts as a bridge between the BUS and the memory.

Discussion

123.	When the USB is connected to a system, its root hub is connected to the ________(a) PCI BUS(b) SCSI BUS(c) Processor BUS(d) IDEThis question was posed to me during an online exam.My question is from USB topic in chapter Input/Output Organisation of Computer Architecture
Answer» CORRECT answer is (c) PROCESSOR BUS The explanation is: The USB’s root is CONNECTED to the processor directly USING the BUS.

Discussion

124.	In USB the devices can communicate with each other.(a) True(b) FalseI had been asked this question during an internship interview.Enquiry is from USB topic in division Input/Output Organisation of Computer Architecture
Answer» Right ANSWER is (b) False Explanation: It ALLOWS only the host to COMMUNICATE with the DEVICES and not between themselves.

Discussion

125.	The data transfer in UART is done in ______(a) Asynchronous start stop format(b) Synchronous start stop format(c) Isochronous format(d) EBDIC formatI have been asked this question during an interview.Question is from Serial Port topic in section Input/Output Organisation of Computer Architecture
Answer» Correct answer is (a) Asynchronous start stop format For explanation I WOULD SAY: This basically means that the data transfer is DONE in asynchronous mode.

Discussion

126.	The serial port is used to connect basically _____ and processor.(a) I/O devices(b) Speakers(c) Printer(d) MonitorThe question was posed to me in semester exam.This intriguing question originated from Serial Port topic in chapter Input/Output Organisation of Computer Architecture
Answer» The correct option is (a) I/O DEVICES Explanation: The SERIAL port is used to CONNECT the keyboard and other devices which input or OUTPUT one bit at a time.

Discussion

127.	Which most popular input device is used today for interactive processing and for the one line entry of data for batch processing?(a) Mouse(b) Magnetic disk(c) Visual display terminal(d) Card punchThis question was addressed to me in examination.Asked question is from Interface Circuits in division Input/Output Organisation of Computer Architecture
Answer» CORRECT choice is (a) Mouse To explain: In batch PROCESSING SYSTEMS the processes are GROUPED into batches and they’re EXECUTED in batches.

Discussion

128.	The Interface circuits generate the appropriate timing signals required by the BUS control scheme.(a) True(b) FalseI had been asked this question in homework.Question is taken from Interface Circuits in chapter Input/Output Organisation of Computer Architecture
Answer» Correct OPTION is (a) True Best explanation: The interface circuits generate the required CLOCK signal for the SYNCHRONOUS MODE of transfer.

Discussion

129.	Distributed arbitration makes use of ______(a) BUS master(b) Processor(c) Arbitrator(d) 4-bit IDThis question was posed to me in an interview.The question is from Bus Arbitration in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT ANSWER is (d) 4-bit ID Explanation: The device uses a 4BIT ID number and based on this the BUS is allocated.

Discussion

130.	In Centralised Arbitration ______ is/are is the BUS master.(a) Processor(b) DMA controller(c) Device(d) Both Processor and DMA controllerThe question was posed to me in unit test.Enquiry is from Bus Arbitration in division Input/Output Organisation of Computer Architecture
Answer» Right ANSWER is (d) Both Processor and DMA controller Explanation: The BUS MASTER is the ONE that decides which will get the BUS.

Discussion

131.	The 8085 microprocessor responds to the presence of an interrupt ___________(a) As soon as the trap pin becomes ‘LOW’(b) By checking the trap pin for ‘high’ status at the end of each instruction fetch(c) By checking the trap pin for ‘high’ status at the end of execution of each instruction(d) By checking the trap pin for ‘high’ status at regular intervalsI got this question in an interview.Origin of the question is Interrupts in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT choice is (c) By checking the trap pin for ‘high’ status at the end of execution of each instruction The BEST explanation: The 8085 MICROPROCESSOR are DESIGNED to complete the execution of the current instruction and then to service the interrupts.

Discussion

132.	______________ register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.(a) Mass(b) Mark(c) Make(d) MaskThis question was posed to me during a job interview.This question is from Interrupts topic in section Input/Output Organisation of Computer Architecture
Answer» The CORRECT CHOICE is (d) Mask Best EXPLANATION: NONE.

Discussion

133.	The technique where the controller is given complete access to main memory is __________(a) Cycle stealing(b) Memory stealing(c) Memory Con(d) Burst modeThis question was addressed to me in exam.I would like to ask this question from Direct Memory Access in chapter Input/Output Organisation of Computer Architecture
Answer» CORRECT choice is (d) BURST mode For explanation: The controller is given FULL control of the memory access cycles and can transfer blocks at a faster RATE.

Discussion

134.	The transmission over the USB is divided into ____(a) Frames(b) Pages(c) Packets(d) TokensThis question was addressed to me by my college director while I was bunking the class.This intriguing question comes from USB in chapter Input/Output Organisation of Computer Architecture
Answer» CORRECT ANSWER is (a) Frames To explain I would SAY: To support the isochronous mode of operation the USB transmission is DIVIDED into frames.

Discussion

135.	DEVSEL# signal is used _________(a) To select the device(b) To list all the devices connected(c) By the device to indicate that it is ready for a transaction(d) None of the mentionedI got this question in an internship interview.My question comes from PCI BUS-2 in portion Input/Output Organisation of Computer Architecture
Answer» Right answer is (c) By the device to INDICATE that it is READY for a transaction Easiest explanation: This is signal is ACTIVATED by the device after it as RECOGNIZED the address and commands put on the BUS.

Discussion

136.	______ to increase the flexibility of the serial ports.(a) The wires used for ports is changed(b) The ports are made to allow different clock signals for input and output(c) The drivers are modified(d) All of the mentionedThis question was posed to me in final exam.This interesting question is from Serial Port topic in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT choice is (b) The ports are made to ALLOW different clock signals for input and output To explain I would SAY: The ports are made more flexible by ENABLING the input or output of different clock signals for different devices.

Discussion

137.	SCSI stands for ___________(a) Signal Computer System Interface(b) Small Computer System Interface(c) Small Coding System Interface(d) Signal Coding System InterfaceThe question was posed to me during an internship interview.I'd like to ask this question from Standard I/O Interfaces in section Input/Output Organisation of Computer Architecture
Answer» Right choice is (B) SMALL Computer SYSTEM Interface Easiest explanation: The SCSI BUS is used to connect disks and video controllers.

Discussion

138.	The BUS busy line is made of ________(a) Open-drain circuit(b) Open-collector circuit(c) EX-Or circuit(d) Nor circuitThe question was asked in a national level competition.My doubt stems from Bus Arbitration topic in chapter Input/Output Organisation of Computer Architecture
Answer» The CORRECT ANSWER is (B) Open-collector circuit Explanation: NONE.

Discussion

139.	The added output of the bits of the interrupt register and the mask register is set as an input of ______________(a) Priority decoder(b) Priority encoder(c) Process id encoder(d) MultiplexerI had been asked this question in a national level competition.The query is from Interrupts topic in chapter Input/Output Organisation of Computer Architecture
Answer» The correct answer is (B) Priority encoder Easy explanation: In a parallel priority system, the priority of the device is obtained by ADDING the contents of the INTERRUPT register and the MASK register.

Discussion

140.	CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged.(a) A hardware interrupt is needed(b) A software interrupt is needed(c) Either hardware or software interrupt is needed(d) A non-privileged instruction (which does not generate an interrupt)is neededI had been asked this question in homework.Query is from Interrupts in portion Input/Output Organisation of Computer Architecture
Answer» Right option is (b) A SOFTWARE INTERRUPT is needed To elaborate: A software interrupt by some PROGRAM which needs some CPU SERVICE, at that time the two modes can be interchanged.

Discussion

141.	The signal sent to the device from the processor to the device after receiving an interrupt is ___________(a) Interrupt-acknowledge(b) Return signal(c) Service signal(d) Permission signalThis question was addressed to me during an interview for a job.My question is from Interrupts topic in division Input/Output Organisation of Computer Architecture
Answer» Correct option is (a) INTERRUPT-acknowledge The EXPLANATION: The Processor upon RECEIVING the interrupt should LET the device know that its request is received.

Discussion

142.	A USB pipe is a ______ channel.(a) Simplex(b) Half-Duplex(c) Full-Duplex(d) Both Simplex and Full-DuplexThe question was posed to me during an interview for a job.This interesting question is from USB topic in chapter Input/Output Organisation of Computer Architecture
Answer» The CORRECT CHOICE is (C) Full-Duplex Best explanation: This MEANS that the PIPE is bi-directional in sending messages or information.

Discussion

143.	When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave.(a) True(b) FalseI got this question in exam.Question is from PCI BUS-1 in section Input/Output Organisation of Computer Architecture
Answer» The correct answer is (b) False Easiest explanation: The address is STORED by the slave in a BUFFER and HENCE it is not required by the MASTER to hold it.

Discussion

144.	______ signal is used to enable commands.(a) FRAME#(b) IRDY#(c) TMY#(d) c/BE#I got this question during an online exam.Asked question is from PCI BUS-2 in chapter Input/Output Organisation of Computer Architecture
Answer» CORRECT option is (d) c/BE# The BEST explanation: The signal is used to enable 4 COMMAND lines.

Discussion

145.	For better transfer rates on the SCSI BUS the length of the cable is limited to ______(a) 2m(b) 4m(c) 1.3m(d) 1.6mI have been asked this question during an interview.My query is from SCSI BUS-2 topic in section Input/Output Organisation of Computer Architecture
Answer» RIGHT CHOICE is (d) 1.6m Explanation: To INCREASE the TRANSMISSION rate in SCSI in SE mode of transfer the wire length is RESTRICTED to 1.6m.

Discussion

146.	______ serves as an intermediary between the device and the BUSes.(a) Interface circuits(b) Device drivers(c) Buffers(d) None of the mentionedThe question was asked during an online interview.Query is from Interface Circuits topic in portion Input/Output Organisation of Computer Architecture
Answer» Correct ANSWER is (a) Interface circuits The explanation is: The interface circuits act as a hardware interface between the device and the SOFTWARE SIDE.

Discussion

147.	The parallel mode of communication is not suitable for long devices because of ______(a) Timing skew(b) Memory access delay(c) Latency(d) None of the mentionedI have been asked this question in my homework.My doubt stems from Interface Circuits topic in division Input/Output Organisation of Computer Architecture
Answer» CORRECT OPTION is (a) Timing skew The best I can EXPLAIN: None.

Discussion

148.	Can a single DMA controller perform operations on two different disks simultaneously?(a) True(b) FalseI have been asked this question by my school teacher while I was bunking the class.I'm obligated to ask this question of Direct Memory Access in portion Input/Output Organisation of Computer Architecture
Answer» The CORRECT OPTION is (a) True Best EXPLANATION: The DMA controller can perform operations on two different disks if the appropriate details are known.

Discussion

149.	The device which interacts with the initiator is __________(a) Slave(b) Master(c) Responder(d) FriendThe question was asked during an internship interview.I would like to ask this question from Synchronous BUS topic in division Input/Output Organisation of Computer Architecture
Answer» CORRECT CHOICE is (a) Slave Explanation: The device which receives the commands from the INITIATOR for data transfer.

Discussion

150.	The Centralised BUS arbitration is similar to ______ interrupt circuit.(a) Priority(b) Parallel(c) Single(d) Daisy chainThe question was asked by my college director while I was bunking the class.I'd like to ask this question from Bus Arbitration topic in section Input/Output Organisation of Computer Architecture
Answer» RIGHT ANSWER is (d) DAISY chain The best explanation: None.

Discussion

Explore topic-wise InterviewSolutions in .

The Master strobes the slave at the end of each clock cycle in Synchronous BUS.(a) True(b) FalseThe question was posed to me in an international level competition.The above asked question is from Synchronous BUS topic in chapter Input/Output Organisation of Computer Architecture

The CRC bits are computed based on the values of the _____(a) PID(b) ADDR(c) ENDP(d) Both ADDR and ENDPI got this question in semester exam.Asked question is from USB in chapter Input/Output Organisation of Computer Architecture

The devices connected to USB is assigned a ____ address.(a) 9 bit(b) 16 bit(c) 4 bit(d) 7 bitThis question was posed to me during an interview for a job.The question is from USB topic in section Input/Output Organisation of Computer Architecture

_____ is used to reset all the device controls to their startup state.(a) SRT(b) RST(c) ATN(d) None of the mentionedI got this question in an online interview.I want to ask this question from SCSI BUS-1 topic in chapter Input/Output Organisation of Computer Architecture

______ address space gives the PCI its plug and plays capability.(a) Configuration(b) I/O(c) Memory(d) All of the mentionedThis question was addressed to me in a job interview.This intriguing question originated from PCI BUS-1 in chapter Input/Output Organisation of Computer Architecture

The _____ circuit enables the generation of the ASCII code when the key is pressed.(a) Generator(b) Debouncing(c) Encoder(d) LoggerI have been asked this question in unit test.This key question is from Parallel Port in division Input/Output Organisation of Computer Architecture

IDE disk is connected to the PCI BUS using ______ interface.(a) ISA(b) ISO(c) ANSI(d) IEEEThis question was addressed to me during an interview for a job.Question is from Standard I/O Interfaces in division Input/Output Organisation of Computer Architecture

The video devices are connected to ______ BUS.(a) PCI(b) USB(c) HDMI(d) SCSIThis question was posed to me during an interview.I would like to ask this question from Standard I/O Interfaces in division Input/Output Organisation of Computer Architecture

A single Interrupt line can be used to service n different devices.(a) True(b) FalseI got this question in an online quiz.My doubt stems from Interrupts topic in chapter Input/Output Organisation of Computer Architecture

_____ provides a separate physical connection to the memory.(a) PCI BUS(b) PCI interface(c) PCI bridge(d) Switch circuitI had been asked this question during an interview.My enquiry is from PCI BUS-1 topic in portion Input/Output Organisation of Computer Architecture

When the USB is connected to a system, its root hub is connected to the ________(a) PCI BUS(b) SCSI BUS(c) Processor BUS(d) IDEThis question was posed to me during an online exam.My question is from USB topic in chapter Input/Output Organisation of Computer Architecture

In USB the devices can communicate with each other.(a) True(b) FalseI had been asked this question during an internship interview.Enquiry is from USB topic in division Input/Output Organisation of Computer Architecture

The data transfer in UART is done in ______(a) Asynchronous start stop format(b) Synchronous start stop format(c) Isochronous format(d) EBDIC formatI have been asked this question during an interview.Question is from Serial Port topic in section Input/Output Organisation of Computer Architecture

The serial port is used to connect basically _____ and processor.(a) I/O devices(b) Speakers(c) Printer(d) MonitorThe question was posed to me in semester exam.This intriguing question originated from Serial Port topic in chapter Input/Output Organisation of Computer Architecture

The Interface circuits generate the appropriate timing signals required by the BUS control scheme.(a) True(b) FalseI had been asked this question in homework.Question is taken from Interface Circuits in chapter Input/Output Organisation of Computer Architecture

Distributed arbitration makes use of ______(a) BUS master(b) Processor(c) Arbitrator(d) 4-bit IDThis question was posed to me in an interview.The question is from Bus Arbitration in portion Input/Output Organisation of Computer Architecture

In Centralised Arbitration ______ is/are is the BUS master.(a) Processor(b) DMA controller(c) Device(d) Both Processor and DMA controllerThe question was posed to me in unit test.Enquiry is from Bus Arbitration in division Input/Output Organisation of Computer Architecture

The transmission over the USB is divided into ____(a) Frames(b) Pages(c) Packets(d) TokensThis question was addressed to me by my college director while I was bunking the class.This intriguing question comes from USB in chapter Input/Output Organisation of Computer Architecture

The BUS busy line is made of ________(a) Open-drain circuit(b) Open-collector circuit(c) EX-Or circuit(d) Nor circuitThe question was asked in a national level competition.My doubt stems from Bus Arbitration topic in chapter Input/Output Organisation of Computer Architecture

A USB pipe is a ______ channel.(a) Simplex(b) Half-Duplex(c) Full-Duplex(d) Both Simplex and Full-DuplexThe question was posed to me during an interview for a job.This interesting question is from USB topic in chapter Input/Output Organisation of Computer Architecture

When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave.(a) True(b) FalseI got this question in exam.Question is from PCI BUS-1 in section Input/Output Organisation of Computer Architecture

______ signal is used to enable commands.(a) FRAME#(b) IRDY#(c) TMY#(d) c/BE#I got this question during an online exam.Asked question is from PCI BUS-2 in chapter Input/Output Organisation of Computer Architecture

For better transfer rates on the SCSI BUS the length of the cable is limited to ______(a) 2m(b) 4m(c) 1.3m(d) 1.6mI have been asked this question during an interview.My query is from SCSI BUS-2 topic in section Input/Output Organisation of Computer Architecture

______ serves as an intermediary between the device and the BUSes.(a) Interface circuits(b) Device drivers(c) Buffers(d) None of the mentionedThe question was asked during an online interview.Query is from Interface Circuits topic in portion Input/Output Organisation of Computer Architecture

The device which interacts with the initiator is __________(a) Slave(b) Master(c) Responder(d) FriendThe question was asked during an internship interview.I would like to ask this question from Synchronous BUS topic in division Input/Output Organisation of Computer Architecture