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151.

The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is?(a) Exceptions(b) Signal handling(c) Interrupts(d) DMAThe question was posed to me in an interview for internship.My doubt stems from Accessing I/O Devices topic in section Input/Output Organisation of Computer Architecture

Answer»

Correct answer is (C) Interrupts

The explanation: This is a method of accessing the I/O devices which gives the COMPLETE power to the devices, enabling them to INTIMATE the processor when they’re ready for TRANSFER.

152.

The best mode of connection between devices which need to send or receive large amounts of data over a short distance is _____(a) BUS(b) Serial port(c) Parallel port(d) Isochronous portThis question was posed to me in unit test.This interesting question is from Parallel Port in section Input/Output Organisation of Computer Architecture

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Right OPTION is (C) Parallel port

Easy explanation: The parallel port transfers around 8 to 16 BITS of data simultaneously over the lines, HENCE increasing transfer rates.

153.

Asynchronous mode of transmission is suitable for systems with multiple peripheral devices.(a) True(b) FalseThis question was addressed to me in my homework.The doubt is from Asynchronous BUS in chapter Input/Output Organisation of Computer Architecture

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The CORRECT CHOICE is (a) True

Easiest explanation: This mode of transmission is suitable for multiple device situation as it SUPPORTS variable SPEED transfer.

154.

The sampling process in speaker output is a ________ process.(a) Asynchronous(b) Synchronous(c) Isochronous(d) None of the mentionedI had been asked this question in a national level competition.This question is from USB in division Input/Output Organisation of Computer Architecture

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Right choice is (c) Isochronous

Easiest EXPLANATION: The isochronous process means each bit of data is SEPARATED by a time INTERVAL.

155.

The BUS that allows I/O, memory and Processor to coexist is _______(a) Attributed BUS(b) Processor BUS(c) Backplane BUS(d) External BUSThe question was asked in homework.Question is taken from Asynchronous BUS topic in portion Input/Output Organisation of Computer Architecture

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Right CHOICE is (c) BACKPLANE BUS

The EXPLANATION is: NONE.

156.

The processor indicates to the devices that it is ready to receive interrupts ________(a) By enabling the interrupt request line(b) By enabling the IRQ bits(c) By activating the interrupt acknowledge line(d) None of the mentionedThe question was asked by my college director while I was bunking the class.This interesting question is from Interrupts topic in chapter Input/Output Organisation of Computer Architecture

Answer» CORRECT ANSWER is (C) By activating the INTERRUPT acknowledge line

To elaborate: When the processor activates the acknowledge line the devices SEND their interrupts to the processor.
157.

In trace mode of operation is ________(a) The program is interrupted after each detection(b) The program will not be stopped and the errors are sorted out after the complete program is scanned(c) There is no effect on the program, i.e the program is executed without rectification of errors(d) The program is halted only at specific pointsThe question was posed to me during an online exam.Question is from Exceptions in division Input/Output Organisation of Computer Architecture

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Correct choice is (a) The program is interrupted after each detection

For explanation I would say: In trace mode, the program is CHECKED LINE by line and if ERRORS are detected then EXCEPTIONS are raised right AWAY.

158.

The MSG signal is used _________(a) To send a message to the target(b) To receive a message from the mailbox(c) To tell that the information being sent is a message(d) None of the mentionedThe question was posed to me in a job interview.Enquiry is from SCSI BUS-1 in portion Input/Output Organisation of Computer Architecture

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Correct CHOICE is (C) To tell that the information being SENT is a message

To explain: None.

159.

The maximum number of devices that can be connected to SCSI BUS is ______(a) 12(b) 10(c) 16(d) 8This question was posed to me by my school principal while I was bunking the class.This key question is from SCSI BUS-2 in section Input/Output Organisation of Computer Architecture

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The CORRECT OPTION is (C) 16

To ELABORATE: NONE.

160.

________ signal is asserted when the initiator wishes to send a message to the target.(a) MSG(b) APP(c) SMS(d) ATNI got this question in unit test.Question is from SCSI BUS-1 topic in division Input/Output Organisation of Computer Architecture

Answer» CORRECT answer is (d) ATN

To elaborate: The ATN SIGNAL is short for attention, which is USED to intimate the target that the initiator sent a MESSAGE to it.
161.

The mode of data transfer used by the controller is _____(a) Interrupt(b) DMA(c) Asynchronous(d) SynchronousThis question was posed to me during an interview.Origin of the question is SCSI BUS-2 in chapter Input/Output Organisation of Computer Architecture

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The CORRECT OPTION is (B) DMA

For EXPLANATION: NONE.

162.

What is DB(P) line?(a) That the data line is carrying the device information(b) That the data line is carrying the parity information(c) That the data line is partly closed(d) That the data line is temporarily occupiedI had been asked this question at a job interview.My question comes from SCSI BUS-1 topic in division Input/Output Organisation of Computer Architecture

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Right ANSWER is (B) That the data line is carrying the parity information

To EXPLAIN: NONE.

163.

_____ signal is sent by the initiator to indicate the duration of the transaction.(a) FRAME#(b) IRDY#(c) TMY#(d) SELD#I had been asked this question in an international level competition.Question is from PCI BUS-2 in portion Input/Output Organisation of Computer Architecture

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Right option is (a) FRAME#

For explanation: The FRAME signal is USED to INDICATE the time required by the DEVICE.

164.

The key features of the SCSI BUS are _________(a) The cost effective connective media(b) The ability overlap data transfer requests(c) The highly efficient data transmission(d) None of the mentionedI have been asked this question in semester exam.The above asked question is from SCSI BUS-1 in division Input/Output Organisation of Computer Architecture

Answer» RIGHT choice is (B) The ability overlap data transfer requests

To EXPLAIN: The SCSI BUS can overlap VARIOUS data transfer requests by the DEVICES.
165.

The system developed by IBM with ISA architecture is ______(a) SPARC(b) SUN-SPARC(c) PC-AT(d) None of the mentionedThe question was asked in quiz.The query is from Standard I/O Interfaces in section Input/Output Organisation of Computer Architecture

Answer» RIGHT ANSWER is (c) PC-AT

To explain I would SAY: NONE.
166.

The key feature of UART is _________(a) Its architectural design(b) Its simple implementation(c) Its general purpose usage(d) Its enhancement of connecting low speed devicesI have been asked this question in an interview for job.Asked question is from Serial Port topic in section Input/Output Organisation of Computer Architecture

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The correct option is (d) Its enhancement of CONNECTING LOW speed devices

Easiest EXPLANATION: NONE.

167.

To resolve the clash over the access of the system BUS we use ______(a) Multiple BUS(b) BUS arbitrator(c) Priority access(d) None of the mentionedThis question was addressed to me by my college director while I was bunking the class.My question is taken from Bus Arbitration topic in division Input/Output Organisation of Computer Architecture

Answer» CORRECT answer is (b) BUS arbitrator

The best explanation: The BUS arbitrator is used to allow a DEVICE to access the BUS based on certain PARAMETERS.
168.

In DMA transfers, the required signals and addresses are given by the __________(a) Processor(b) Device drivers(c) DMA controllers(d) The program itselfThis question was posed to me during an interview for a job.The query is from Direct Memory Access topic in chapter Input/Output Organisation of Computer Architecture

Answer» CORRECT option is (c) DMA controllers

The explanation is: The DMA controller acts as a processor for DMA TRANSFERS and OVERLOOKS the ENTIRE process.
169.

A privilege exception is raised __________(a) When a process tries to change the mode of the system(b) When a process tries to change the priority level of the other processes(c) When a process tries to access the memory allocated to other users(d) All of the mentionedThe question was posed to me during an internship interview.Origin of the question is Exceptions in chapter Input/Output Organisation of Computer Architecture

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Right OPTION is (d) All of the mentioned

To EXPLAIN I WOULD SAY: None.

170.

The first field of any packet is _____(a) PID(b) ADDR(c) ENDP(d) CRC16This question was addressed to me in an interview for job.This key question is from USB topic in section Input/Output Organisation of Computer Architecture

Answer» RIGHT option is (a) PID

Easy explanation: The PID is the field that is USED to identify the DEVICE (the device ID).
171.

The _____ signal is used to indicate the beginning of a new frame.(a) Start(b) SOF(c) BEG(d) None of the mentionedThe question was posed to me at a job interview.Question is from USB topic in portion Input/Output Organisation of Computer Architecture

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The correct ANSWER is (b) SOF

Easiest explanation: The SOF(State Of Frame) is used to INDICATE the beginning of a NEW frame.

172.

Locations in the device to or from which data transfers can take place is called ________(a) End points(b) Hosts(c) Source(d) None of the mentionedI have been asked this question by my school principal while I was bunking the class.I'd like to ask this question from USB in division Input/Output Organisation of Computer Architecture

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The CORRECT ANSWER is (a) END points

For EXPLANATION I would say: NONE.

173.

The USB device follows _______ structure.(a) List(b) Huffman(c) Hash(d) TreeThe question was asked by my college director while I was bunking the class.This is a very interesting question from USB in section Input/Output Organisation of Computer Architecture

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The CORRECT choice is (d) TREE

Easy explanation: The USB has a tree structure with the ROOT hub at the centre.

174.

SCSI stands for ________(a) Small Computer System Interface(b) Switch Computer system Interface(c) Small Component System Interface(d) None of the mentionedI got this question by my college director while I was bunking the class.I would like to ask this question from SCSI BUS-2 in division Input/Output Organisation of Computer Architecture

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Correct OPTION is (a) SMALL COMPUTER System Interface

The best explanation: The SCSI BUS is one of the EXPANSION BUSes USED in a system.

175.

The SEL signal signifies _________(a) The initiator is selected(b) The device for BUS control is selected(c) That the target is being selected(d) None of the mentionedI got this question in exam.The query is from SCSI BUS-1 in portion Input/Output Organisation of Computer Architecture

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Right option is (B) The device for BUS control is selected

The EXPLANATION is: This signal is USUALLY ASSERTED during the selection or reselection process.

176.

A complete transfer operation over the BUS, involving the address and a burst of data is called _____(a) Transaction(b) Transfer(c) Move(d) ProcedureThe question was asked in my homework.My question is from PCI BUS-2 topic in chapter Input/Output Organisation of Computer Architecture

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The CORRECT OPTION is (a) Transaction

Easy EXPLANATION: NONE.

177.

The standard used in serial ports to facilitate communication is _____(a) RS-246(b) RS-LNK(c) RS-232-C(d) Both RS-246 and RS-LNKI had been asked this question in examination.I want to ask this question from Serial Port in section Input/Output Organisation of Computer Architecture

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The correct CHOICE is (c) RS-232-C

Explanation: This is a standard that ACTS as a protocol for message COMMUNICATION involving SERIAL ports.

178.

DDR stands for __________(a) Data Direction Register(b) Data Decoding Register(c) Data Decoding Rate(d) None of the mentionedI have been asked this question in quiz.Enquiry is from Parallel Port in chapter Input/Output Organisation of Computer Architecture

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The CORRECT ANSWER is (a) Data DIRECTION REGISTER

Easy explanation: This register is used to control the flow of data from the DATAOUT register.

179.

After the device completes its operation _____ assumes the control of the BUS.(a) Another device(b) Processor(c) Controller(d) None of the mentionedThis question was posed to me in class test.This intriguing question comes from Bus Arbitration in division Input/Output Organisation of Computer Architecture

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Right OPTION is (B) Processor

Easiest EXPLANATION: After the device COMPLETES the operation it releases the BUS and the processor TAKES over it.

180.

When the R/W bit of the status register of the DMA controller is set to 1.(a) Read operation is performed(b) Write operation is performed(c) Read & Write operation is performed(d) None of the mentionedI got this question in unit test.The origin of the question is Direct Memory Access topic in chapter Input/Output Organisation of Computer Architecture

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Right ANSWER is (a) Read operation is performed

For EXPLANATION I would say: NONE.

181.

The resistor which is attached to the service line is called _____(a) Push-down resistor(b) Pull-up resistor(c) Break down resistor(d) Line resistorI have been asked this question during an interview for a job.I'm obligated to ask this question of Interrupts in section Input/Output Organisation of Computer Architecture

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Correct choice is (B) PULL-up RESISTOR

The explanation: This resistor is used to pull up the voltage of the INTERRUPT service line.