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Cloud architecture provide LARGE pool of DYNAMIC resources that can be accessed any time whenever there is a requirement, which is not being given by the TRADITIONAL architecture. In traditional architecture it is not possible to dynamically associate a machine with the rising demand of infrastructure and the services. Cloud architecture provides scalable PROPERTIES to meet the high demand of infrastructure and provide on-demand access to the user.

Cloud architecture provide large pool of dynamic resources that can be accessed any time whenever there is a requirement, which is not being given by the traditional architecture. In traditional architecture it is not possible to dynamically associate a machine with the rising demand of infrastructure and the services. Cloud architecture provides scalable properties to meet the high demand of infrastructure and provide on-demand access to the user.

For any computer GENERALLY the MEMORY space is LESSER as compared to the address space this implies that the MAIN memory is lesser as compared to the secondary memory.

For any computer generally the memory space is lesser as compared to the address space this implies that the main memory is lesser as compared to the secondary memory.

PARTITIONING involves the user to partition their HARD drives and then they can implement / install multiple OPERATING systems on them. The user REQUIRES a boot MANAGER to switch between different operating systems.

Partitioning involves the user to partition their hard drives and then they can implement / install multiple operating systems on them. The user requires a boot manager to switch between different operating systems.

In a WAY virtualization appears similar to emulation but ACTUALLY it shares hardware resources from the host OS.

• This METHOD is slower as compared to partition method but is faster than emulation.
• Virtualization had also vast SUPPORT considering it can also provide with 3d support.
• With the help of virtualization it enable users to create virtual clusters.
• But virtualization systems require a lot of memory in form of ram.
• For virtualization it is mandatory that the VIRTUALIZED platform has the same architecture as the host pc otherwise due to incompatibilities it is not possible.

In a way virtualization appears similar to emulation but actually it shares hardware resources from the host OS.

• ALTHOUGH Assembly level languages are not easy to understand they are RELATIVELY EASIER as compared to machine level languages.
• The programs written in this language are not portable and the DEBUGGING process is also not very easy.
• The programs DEVELOPED in assembly language are thoroughly machine dependent.

• In case of vertical MICRO code every action is encoded in DENSITY.
• Vertical micro code are slower but they take LESS space and their actions at execution TIME need to be decoded to a SIGNAL.

In direct mapping the RAM is made use of to store data and some is STORED in the cache. An address space is split into two PARTS index field and tag field. The cache is used to store the tag field whereas the rest is stored in the main memory. Direct mapping`s PERFORMANCE is directly PROPORTIONAL to the Hit ratio.

In direct mapping the RAM is made use of to store data and some is stored in the cache. An address space is split into two parts index field and tag field. The cache is used to store the tag field whereas the rest is stored in the main memory. Direct mapping`s performance is directly proportional to the Hit ratio.

In this TYPE of mapping the associative MEMORY is USED to store content and addresses both of the memory word. This enables the placement of the any word at any PLACE in the cache memory. It is considered to be the fastest and the most flexible mapping FORM.

In this type of mapping the associative memory is used to store content and addresses both of the memory word. This enables the placement of the any word at any place in the cache memory. It is considered to be the fastest and the most flexible mapping form.

In this method only the location in the cache is UPDATED. Whenever such an update OCCURS a FLAG is set which makes sure that in case the word is removed from the cache the correct copy is SAVED to the main memory. This approach is USUALLY taken when a word is constantly updated at frequent intervals.

In this method only the location in the cache is updated. Whenever such an update occurs a flag is set which makes sure that in case the word is removed from the cache the correct copy is saved to the main memory. This approach is usually taken when a word is constantly updated at frequent intervals.

Considered to be the simplest this method involves the updating of the main memory CORRESPONDING to every write operation. With this the CACHE memory is also UPDATED in parallel in CASE it also contains the WORD specified at the address. The primary advantage of this method is data integrity, the primary and the cache memory both contain the same data.

Considered to be the simplest this method involves the updating of the main memory corresponding to every write operation. With this the cache memory is also updated in parallel in case it also contains the word specified at the address. The primary advantage of this method is data integrity, the primary and the cache memory both contain the same data.

The micro-operations in computers are classified into the following categories:

Register transfer micro-operations: These type of micro operations are used to transfer from one register to another binary information.
Arithmetic micro-operations: These micro-operations are used to perform on numeric data stored in the REGISTERS some arithmetic operations.
Logic micro-operations: These micro operations are used to perform bit style operations / MANIPULATIONS on non numeric data.
Shift micro operations: As their NAME suggests they are used to perform shift operations in data STORE in registers.

The micro-operations in computers are classified into the following categories:

Register transfer micro-operations: These type of micro operations are used to transfer from one register to another binary information.
Arithmetic micro-operations: These micro-operations are used to perform on numeric data stored in the registers some arithmetic operations.
Logic micro-operations: These micro operations are used to perform bit style operations / manipulations on non numeric data.
Shift micro operations: As their name suggests they are used to perform shift operations in data store in registers.

An instruction can be considered to be a command that has been issued to a COMPUTER to perform a particular operation. The instruction format contains various field in them such as:

• Operation Code Field: Also known as the op code field, this field is used to specify the operation to be performed for the instruction.
• Address Field: This field as its name specifies is used to DESIGNATE the various addresses such as REGISTER address and memory address.
• Mode field: This field specifies as to how effective address is derives or how an operand is to perform.

For ex: ADD R0, R1. In this case the ADD is the operand whereas the R1, ans R0 are the address fields.

An instruction can be considered to be a command that has been issued to a computer to perform a particular operation. The instruction format contains various field in them such as:

For ex: ADD R0, R1. In this case the ADD is the operand whereas the R1, ans R0 are the address fields.

The following are the main reasons for pipe line conflicts in the PROCESSOR:

• When the same resource is ACCESSED at the same time by two different segments it results in resource conflicts. The only way to RESOLVE this PROBLEM is to use separate data memories.
• In case an instruction's execution depends on the result of a previous instruction and that result is unavailable it leads to data dependency conflicts.
• Instructions that change the count of the PC can cause a lot of problems. This is prevalent particularly in the case of Branch instructions. A method to resolve this issue is known as delayed load where certain instruction are made to execute in a delayed MANNER to avoid conflicts.

The following are the main reasons for pipe line conflicts in the processor:

The main components of the Von Neumann architecture were as FOLLOWS:

• It consisted of a main MEMORY which would be used to store all the data and instructions.
• It would consist of an arithmetic logical unit also known as the ALU. This part was to be able to work with binary data.
• It also COMPRISED of a control unit which would be RESPONSIBLE for the interpretation of instructions and their execution.
• The control unit would also be CONTROLLED by the control unit itself.

The main components of the Von Neumann architecture were as follows:

Some of the common RULES of assembly level LANGUAGE are as follows:

• In assembly language the LABEL field can be either empty or may specify a symbolic address.
• Instruction FIELDS can specify pseudo or machine instructions.
• Comment fields can be left empty or can be commented with.
• Up to 4 characters are only allowed in the case of symbolic addresses.
• The symbolic addresses field are terminated by a comma WHEREAS the comment field begins with a forward slash.

Some of the common rules of assembly level language are as follows:

Two different ways of establishing HARDWARE priority are Daisy Chaining and parallel priority.

• Daisy chaining is a FORM of a hardware implementation of the polling procedure.
• Parallel priority is quicker of the two and uses a priority encoder to establish priorities.
• In parallel priority interrupt a register is used for which the bits are separated by the interrupt signals from every device.
• The parallel priority interrupt may ALSO contain a mask register which is primarily used to control the status of every request regarding INTERRUPTS.

Two different ways of establishing hardware priority are Daisy Chaining and parallel priority.

• A no operation NOP can be included in each FIELD if necessary.
• The remaining micro operations can be distributed AMONG the other operation field BITS.
• Also micro operations that MODIFY the same registers COULD be grouped together in the same field.

Vertical MICROCODE can be CONSIDERED to be a segment of CODE or operators that have been clubbed together into fields. In this field EVERY micro OPERATION is given a unique value.

Vertical microcode can be considered to be a segment of code or operators that have been clubbed together into fields. In this field every micro operation is given a unique value.

These TYPES if interrupts can occur only during the execution of an instruction. They can be used by a PROGRAMMER to cause interrupts if need be. The primary purpose of such interrupts is to switch from USER mode to supervisor mode.

These types if interrupts can occur only during the execution of an instruction. They can be used by a programmer to cause interrupts if need be. The primary purpose of such interrupts is to switch from user mode to supervisor mode.

Emulation is the process in which a target CPU and its corresponding hardware WOULD be emulated exactly the same way.

• Emulation is a relatively old concept and is not widely used to emulate full scale OS usage.
• It is considered to be the best platform for embedded/os development.
• Emulation is possible for any hardware and it does not affect the underlying OS ( host ).
• Although there are many positives of emulation there are few downside of it as well, Emulation can be extremely SLOW.
• Complete thorough hardware support cannot be possible in emulation.
• Emulation is also very resource hungry and REQUIRES a LOT of RAM to function smoothly.

Emulation is the process in which a target CPU and its corresponding hardware would be emulated exactly the same way.

They are also known as traps and their causes could be due to some illegal OPERATION or the erroneous use of data. Instead of being triggered by an external event they are usually triggered due to any exception that has been caused by the PROGRAM itself. Some of the causes of these types of interrupts can be due to attempting a division by zero or an INVALID opcode ETC.

They are also known as traps and their causes could be due to some illegal operation or the erroneous use of data. Instead of being triggered by an external event they are usually triggered due to any exception that has been caused by the program itself. Some of the causes of these types of interrupts can be due to attempting a division by zero or an invalid opcode etc.

The different types of instructions are as follows:

• Immediate MODE: As the NAME suggests the INSTRUCTION in itself contains the operand.
• Register Mode: In this mode the operands of an instruction are PLACED in the registers which themselves are placed inside the CPU.
• Direct address mode: The address part of an instruction in this mode is the effective address.
• Indexed addressing mode: In this mode in order to obtain the effective address the contents of the INDEX register is added to the instructions address part.
• Relative address mode: In this mode in order to find out the effective address the contents of the program counter are added to the address part of the instruction.

The different types of instructions are as follows:

These TYPES of INTERRUPTS generally come from external input / OUTPUT devices which are connected externally to the PROCESSOR. They are generally independent and oblivious of any programming that is CURRENTLY running on the processor.

These types of interrupts generally come from external input / output devices which are connected externally to the processor. They are generally independent and oblivious of any programming that is currently running on the processor.

The main components of the Von Neumann architecture were as follows:

• It consisted of a main memory which would be USED to store all the data and instructions.
• It would consist of an arithmetic logical unit also known as the ALU. This PART was to be able to work with binary data.
• It also COMPRISED of a control unit which would be responsible for the INTERPRETATION of instructions and their execution.
• The control unit would also be controlled by the control unit itself.

The main components of the Von Neumann architecture were as follows:

The instruction sets can be differentiated by:

• OPERAND storage in the CPU
• NUMBER of EXPLICIT operands per instruction
• Operand location
• Operations
• Type and size of operands

The instruction sets can be differentiated by:

Any program residing in the memory contains a set of instruction that need to be executed by the computer in a sequential MANNER. This cycle for EVERY instruction is known as the instruction cycle . The cycle consists of the following steps:

• Fetch instruction: Like the name stated in this process the cpu fetches the instruction from the memory. The PC get loaded with the address of the instruction.
• Decode: the instruction: In this process the instruction gets decoded by the PROCESSOR.In case the instruction has an indirect address the effective address is READ from the memory.Fetch the operand from the memory
• Execution: once the instruction gets decoded the processor executes the instruction.
• RESULT: Store the result in the appropriate place.

Any program residing in the memory contains a set of instruction that need to be executed by the computer in a sequential manner. This cycle for every instruction is known as the instruction cycle . The cycle consists of the following steps:

Snooping is the process where the individual CACHES monitor address lines for accesses to memory LOCATIONS that they have cached. When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location.

Snarfing is where a cache controller watches both address and data in an ATTEMPT to update its own copy of a memory location when a second master modifies a location in MAIN memory

Snooping is the process where the individual caches monitor address lines for accesses to memory locations that they have cached. When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location.

Snarfing is where a cache controller watches both address and data in an attempt to update its own copy of a memory location when a second master modifies a location in main memory

RISC meaning reduced instruction set as the ACRONYM say aims to reduce the execution times of instructions by simplifying the instructions.

The major characteristics of RISC are as follows:

• Compared to normal instructions they have a lower NUMBER of instructions.
• The addressing modes in case of RISC is also lower.
• All the operations that are required to be performed take place within the CPU.
• All instruction are executed in a single cycle hence have a faster execution time.
• in this architecture the processors have a large number of registers and a much more EFFICIENT instruction pipeline.
• Also the instruction formats are of fixed LENGTH and can be easily DECODED.

RISC meaning reduced instruction set as the acronym say aims to reduce the execution times of instructions by simplifying the instructions.

The major characteristics of RISC are as follows:

The MESI protocol is also known as Illinois protocol due to its DEVELOPMENT at the University of Illinois at Urbana-Champaign and MESI is a widely used cache coherency and memory COHERENCE protocol.

MESI is the most common protocol which SUPPORTS write-back cache. Its use in personal computers became WIDESPREAD with the INTRODUCTION of Intel's Pentium processor to "support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor"

The MESI protocol is also known as Illinois protocol due to its development at the University of Illinois at Urbana-Champaign and MESI is a widely used cache coherency and memory coherence protocol.

MESI is the most common protocol which supports write-back cache. Its use in personal computers became widespread with the introduction of Intel's Pentium processor to "support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor"

The following are the main reasons for pipe line conflicts in the processor:

• When the same resource is accessed at the same TIME by two different segments it results in resource conflicts. The only way to resolve this problem is to use separate data memories.
• In case an instruction's execution depends on the result of a previous instruction and that result is unavailable it leads to data dependency conflicts.
• Instructions that change the count of the PC can cause a lot of problems. This is prevalent particularly in the case of BRANCH instructions. A method to resolve this issue is known as delayed load where certain instruction are MADE to execute in a delayed manner to avoid conflicts.

The following are the main reasons for pipe line conflicts in the processor:

An instruction can be considered to be a COMMAND that has been issued to a computer to perform a particular operation.

The instruction format contains various field in them such as:

Operation CODE Field: Also known as the op code field, this field is used to specify the operation to be PERFORMED for the instruction.
Address Field: This field as its name specifies is used to designate the various addresses such as register address and memory address.
Mode field: This field specifies as to how effective address is derives or how an operand is to perform.
For ex:. ADD R0, R1. In this CASE the ADD is the operand whereas the R1, ANS R0 are the address fields.

An instruction can be considered to be a command that has been issued to a computer to perform a particular operation.

The instruction format contains various field in them such as:

Operation Code Field: Also known as the op code field, this field is used to specify the operation to be performed for the instruction.
Address Field: This field as its name specifies is used to designate the various addresses such as register address and memory address.
Mode field: This field specifies as to how effective address is derives or how an operand is to perform.
For ex:. ADD R0, R1. In this case the ADD is the operand whereas the R1, ans R0 are the address fields.

1. ADDRESS lines to refer to the address of a block
2. DATA lines for data transfer
3. IC CHIPS 4 PROCESSING data

In a way virtualization appears SIMILAR to EMULATION but actually it shares HARDWARE resources from the host OS.

• This method is SLOWER as compared to partition method but is faster than emulation.
• Virtualization had also vast support considering it can also provide with 3d support.
• With the help of virtualization it enable users to create virtual clusters.
• But virtualization systems require a lot of memory in form of ram.
• For virtualization it is mandatory that the virtualized platform has the same architecture as the host pc otherwise due to incompatibilities it is not POSSIBLE.

In a way virtualization appears similar to emulation but actually it shares hardware resources from the host OS.

Subroutine are the part of executing processes(LIKE any PROCESS can CALL a subroutine for achieve TASK),while the INTERRUPT subroutine never be the part.interrupt subroutine are subroutine that are external to a process.

Subroutine are the part of executing processes(like any process can call a subroutine for achieve task),while the interrupt subroutine never be the part.interrupt subroutine are subroutine that are external to a process.

PARTITIONING involves the USER to partition their hard drives and then they can implement / install multiple operating systems on them. The user requires a boot manager to switch between different operating systems.

• Partitioning allows each operating SYSTEM to work optimally.
• Each os has the complete access to the HARDWARE of the system on which it is being executed.
• Also depending on the file system used the user is free to resize his partition according to his needs.
• But manual partition is not a simple task and requires patience.
• The system needs to be restarted in case the user WANTS to switch operating systems.

Partitioning involves the user to partition their hard drives and then they can implement / install multiple operating systems on them. The user requires a boot manager to switch between different operating systems.

Like java have a feature for HANDLING EXCEPTION handling "PRIME CATCH".the exception like DIVIDE by zero,out of bound.

Like java have a feature for handling exception handling "prime catch".the exception like divide by zero,out of bound.

Flip flops are also known as bi-stable multi-vibrators. They are able to store one bit of DATA.

• Flip flops are able to be in two stable states namely one and zero. They can be in either states and in order to change their states they have to be driven by a trigger.
• Certain flip flops are edge triggered MEANING they only respond to voltage changes from one LEVEL to another. They can be either positive edged triggering or negative edged triggering.
• Flip flops turn on in a random manner that is they can be in either of the states when they are turned on. In order to have a uniform state when they are POWERED on a CLEAR signal has to be SENT to the flip flops. They can also be made to turn on in a particular state by applying PRESET.

Flip flops are also known as bi-stable multi-vibrators. They are able to store one bit of data.

• ARISE a non maskable interrupt.
• Then give JUMP INSTRUCTION to REQUIRED subroutine.

For any computer generally the MEMORY space is lesser as compared to the ADDRESS space this implies that the main memory is lesser as compared to the secondary memory.

• On the BASIS of the demands of the CPU data is transferred between the two memories.
• Due to this a mapping technique is required which can be implemented using page-table.
• The page table can be organized in two ways namely in the R/W memory and by using associative logic.
• In case of R/W memory the speed of execution of programs is slow as it requires two main memory references to read data. It is also known as memory page table.
• In case of associative logic it is considered to be more effective because it can be built with simply keeping mind to have equal no. of blocks in the memory as many as there are words.

For any computer generally the memory space is lesser as compared to the address space this implies that the main memory is lesser as compared to the secondary memory.

The latency of the ARCHITECTURE INCREASES with the PIPELINE stages. Penalty due to the flushing of the pipeline for instance will also increase CYCLES Per Instruction of the CPU architecture

The latency of the architecture increases with the pipeline stages. Penalty due to the flushing of the pipeline for instance will also increase Cycles Per Instruction of the CPU architecture

Two different ways of establishing HARDWARE priority are Daisy Chaining and parallel priority.

• Daisy chaining is a form of a hardware implementation of the polling procedure.
• Parallel priority is quicker of the two and uses a priority encoder to establish priorities.
• In parallel priority interrupt a REGISTER is used for which the bits are SEPARATED by the interrupt signals from every device.
• The parallel priority interrupt may also contain a mask register which is PRIMARILY used to control the status of every REQUEST regarding interrupts.

Two different ways of establishing hardware priority are Daisy Chaining and parallel priority.

There are situations, CALLED hazards, that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining.

There are three classes of Hazards:

1. STRUCTURAL Hazards: It arise from resource conflicts when the hardware cannot SUPPORT all possible COMBINATIONS of instructions simultaniously in ovelapped execution.
2. Data Hazards: It arise when an instruction depends on the results of previous instruction in a way that is exposed by the ovelapping of instructions in the pipeline.
3. Control Hazards: It arise from the pipelining of branches and other instructions that CHANGE the PC.

There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining.

There are three classes of Hazards:

Vertical microcode can be considered to be a SEGMENT of CODE or operators that have been clubbed TOGETHER into fields. In this field every micro operation is given a unique value.

• This helps in efficient organization of related code together.
• An effective design strategy could be in case of 2 micro operations occurring at the same state, to assign them two different fields.
• A no operation NOP can be included in each field if necessary.
• The remaining micro operations can be distributed among the other operation field bits.
• Also micro operations that modify the same REGISTERS could be grouped together in the same field.

Vertical microcode can be considered to be a segment of code or operators that have been clubbed together into fields. In this field every micro operation is given a unique value.

computer have different type of memory LIKE primary memory , AUXILIARY memory , buffer memory , Cache memory , virtual memory ,the work of all memory heterogeneously primary memory is directly communicate with the CPU . Auxiliary memory are used for storing the data for long time . Buffer memory are mainly used for storing the intermediate data between the TRAVEL . cache memory are used for storing the those data that currently required at process time for increase the SPEED of the data . virtual memory are put in between the two memory for increase the speed of data or instruction it means it put between HDD and RAM .

computer have different type of memory like primary memory , Auxiliary memory , buffer memory , Cache memory , virtual memory ,the work of all memory heterogeneously primary memory is directly communicate with the CPU . Auxiliary memory are used for storing the data for long time . Buffer memory are mainly used for storing the intermediate data between the travel . cache memory are used for storing the those data that currently required at process time for increase the speed of the data . virtual memory are put in between the two memory for increase the speed of data or instruction it means it put between HDD and RAM .

Some of the common rules of ASSEMBLY level language are as follows:

• In assembly language the label field can be either empty or may specify a symbolic address.
• Instruction fields can specify pseudo or machine instructions.
• Comment fields can be left empty or can be commented with.
• Up to 4 characters are only ALLOWED in the CASE of symbolic addresses.
• The symbolic addresses field are terminated by a comma whereas the comment field begins with a FORWARD slash.

Some of the common rules of assembly level language are as follows:

Virtual MEMORY is that when the available RAM memory is not sufficient for the system to run the current APPLICATIONS it will TAKE some memory from hard disk.This memory is termed as Virtual memory.

Virtual memory is that when the available RAM memory is not sufficient for the system to run the current applications it will take some memory from hard disk.This memory is termed as Virtual memory.

In the normal EXECUTION of a program there are three TYPES of interrupts that can cause a break:

External Interrupts: These types of interrupts generally come from external input / output devices which are connected externally to the processor. They are generally independent and OBLIVIOUS of any programming that is currently running on the processor.

Internal Interrupts: They are also known as traps and their causes could be due to some illegal operation or the ERRONEOUS use of data. Instead of being TRIGGERED by an external event they are usually triggered due to any exception that has been caused by the program itself. Some of the causes of these types of interrupts can be due to attempting a division by zero or an invalid opcode etc.

Software interrupts: These types if interrupts can occur only during the execution of an instruction. They can be used by a programmer to cause interrupts if need be. The primary purpose of such interrupts is to switch from user mode to supervisor mode.

In the normal execution of a program there are three types of interrupts that can cause a break:

External Interrupts: These types of interrupts generally come from external input / output devices which are connected externally to the processor. They are generally independent and oblivious of any programming that is currently running on the processor.

Internal Interrupts: They are also known as traps and their causes could be due to some illegal operation or the erroneous use of data. Instead of being triggered by an external event they are usually triggered due to any exception that has been caused by the program itself. Some of the causes of these types of interrupts can be due to attempting a division by zero or an invalid opcode etc.

Software interrupts: These types if interrupts can occur only during the execution of an instruction. They can be used by a programmer to cause interrupts if need be. The primary purpose of such interrupts is to switch from user mode to supervisor mode.