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Right answer is (a) 15

For explanation: The level 15 of the SPARC processor is assigned to be a nonmaskable INTERRUPT and the REMAINING 14 levels are unmasked and if NECESSARY they can be made maskable.

The CORRECT choice is (c) 64

Explanation: There are three major VERSIONS of SPARC which are SPARC-V7, SPARC-V8 and SPARC-V9. The former two are 32 bits processor and the later is a 64-bit processor.

Right choice is (a) LOAD and store instruction

Explanation: The DATA of memory ADDRESS is loaded into a REGISTER and manipulated, its CONTENTS are written out to the main memory.

The correct CHOICE is (C) By using stack segment register

Easy EXPLANATION: Stack segment register is a SPECIAL register that INDEXES into the stack.

Correct answer is (B) Storing data and performing arithmetic and logical OPERATIONS

The explanation: Accumulator is used for all the arithmetic operations such as addition, SUBTRACTION, multiplication, as well as relational & logical operations.

The correct ANSWER is (a) 8080

Best EXPLANATION: 8086 was released in 1978 and 8088 was released in 1979. 8087 is a NUMERIC coprocessor that was released in 1977. Furthermore, 8080 is a device designed by Intel in 1974.

The correct answer is (C) 24

To explain: AAU have 24 address REGISTERS in three banks of eight.

The correct answer is (b) 3

The best I can explain: It possess THREE separate external buses, ONE is for the program and the remaining two buses are for X and Y MEMORIES for DATA.

Correct option is (b) IBM

The BEST explanation: In 1970S IBM identified RISC ARCHITECTURE.

The CORRECT ANSWER is (a) David Patterson

To elaborate: David Patterson of Berkeley university coined the TERM RISC whereas Michael J Flynn who FIRST views RISC.

Correct choice is (b) 5 MHz

The BEST I can explain: 8087 have 5 MHz as its clock FREQUENCY because the coprocessor MUST have the same clock frequency as that of the MAIN processor.

Right option is (a) AH,AL

Easiest explanation: The 16 BIT REGISTER of 80286 can also ACT as 8 bit register by SPLITTING into a higher register and lower register.

The correct answer is (d) 6

The explanation is: 6 is the interrupt vector indicating INVALID OPCODE. It will be different for a different MICROPROCESSOR.

The correct CHOICE is (a) Paging

For explanation: The 80286 processor can access beyond 1MB by paging and special hardware to STIMULATE the MISSING ADDRESS lines. This is called EXPANDED memory.

The CORRECT CHOICE is (d) 80386

To explain I would say: The first generation of INTEL started with 80386 which had 32-bit REGISTERS.

Right choice is (b) AS,BS,CS,DS

For explanation I would say: Intel 80286 possess 4 GENERAL purpose registers, 4 SEGMENTED registers, 2 index register and a base POINTER register.

Right option is (B) 2

Easy explanation: MC6800 is having 2 ACCUMULATORS both comprising of 8 bits.

Right choice is (a) IU, FPU, CU

Easy EXPLANATION: The SPARC processor has three modules which are INTEGER unit, FLOATING point unit, and coprocessor unit. Each module has its own functions and integer unit controls the overall OPERATION of the processor.

Correct OPTION is (c) Intel Pentium

To elaborate: Intel Pentium have many advanced features ONE of which is, it can EXECUTE two instructions per cycle thus improving the speed of the PROCESSOR whereas 80486, 80386 and 80386DX does not have this FEATURE.

The correct OPTION is (b) 8

For explanation: While an interrupt cycle is running, the processor possesses two INTERRUPTS to acknowledge bus cycles and reads an 8-bit vector number. This vector is then used to LOCATE, within the vector table and it has the address of the corresponding interrupt service routine. NMI is automatically ASSIGNED as vector number 2.

The correct CHOICE is (c) BANDWIDTH

Explanation: The bandwidth of any FILTER depends on the speed of operations held in a DIGITAL signal processor.

The CORRECT answer is (d) sun microsystem

Best explanation: SPARC is developed by Sun Microsystem but different MANUFACTURERS from other COMPANIES like INTEL, Texas WORKED on it.

Correct choice is (b) Stack

Explanation: Stack can be used at the time of function CALL or it is a SHORT time large-scale storage of data. THEREFORE, a stack is an area WITHIN MEMORY for storage.

Correct choice is (a) IU

For explanation I would say: Integer UNIT contains the GENERAL purpose registers and it controls the overall operation and performance of the processor and the memory ADDRESS is ALSO CALCULATED by the integer unit.

The correct CHOICE is (a) 16 128-bit

For explanation I would say: It possesses 32 32-bit single PRECISION, 32 64-bit DOUBLE precision and 16 128-bit quads precise floating registers.

Right option is (d) PENTIUM pro

The explanation: SPECULATIVE execution is executed speculatively that is, following the predicted BRANCH paths in the code until the true path is DETERMINED. If the PROCESSOR executes correctly, then the performance is gained, if not, the results are discarded and the processor continues to execute until the correct path is identified.

Right answer is (B) address arithmetic unit

For explanation I would say: DSP56000 POSSESS two external bus SWITCHES in which one is for data and the other is for the address for COMMUNICATING with the outside world and these two switches are REPRODUCED by the internal data bus and AAU.

The correct OPTION is (b) Motorola DSP56000

Easiest explanation: Motorola DSP56000 is a POWERFUL digital SIGNAL processor which is used in digital audio APPLICATIONS which have the capability of noise reduction and multi-band graphics whereas 8087 is a COPROCESSOR and 80486 and 8086 are microprocessors.

The correct CHOICE is (a) low bandwidth

Easy explanation: Loop control timing varies depending on the branch predictions which in TURN MAKE bandwidth predictions difficult thereby lowering the bandwidth of the digital SIGNAL processor.

The correct choice is (a) SPARC

The EXPLANATION is: SPARC and MIPS processors are the FIRST generation processors of RISC ARCHITECTURE.

Correct option is (b) 80386SX

For explanation I would say: Derivative of the 80386DX called the 80386SX which provides the same ARCHITECTURE and lowers cost. To minimal the cost value, it uses an external 16-bit DATA bus and a 24-bit memory bus.

The CORRECT option is (a) Fetch, decode, execute

To elaborate: The instruction can execute in a SINGLE cycle which is DONE by pipelining the instruction flow. The address calculations are performed as the instruction PROCEEDS down the line. Pipelining may take several cycles, an instruction can potentially be started and completed on every clock EDGE, thus achieving the single cycle performance.

The CORRECT answer is (a) instruction-level parallelism

Best explanation: A PROCESSOR which supports instruction-level parallelism can PERFORM multiple independent operations in every instruction cycle. Basically, there are FOUR TYPES of instructions. These are CISC instructions, subword parallelism, superscalar, and VLIW.

The correct option is (c) 15

The explanation is: SPARC processor provides 15 EXTERNAL INTERRUPTS which are generated by the INTERRUPT LINES IRL0-IRL3.

Right option is (b) 80486

To explain: 80486 have a five stage pipeline ALU. These include FETCH, DECODE, execute, MEMORY access and WRITE back. This helps in accessing instruction faster and thus makes the PROCESSOR faster. 80386DX have a three-stage pipelining which only includes fetch, decode and execute.