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This section includes InterviewSolutions, each offering curated multiple-choice questions to sharpen your knowledge and support exam preparation. Choose a topic below to get started.

1.

If M denotes the number of memory locations and N denotes the word size, then an expression that denotes the storage capacity is ______________(a) M*N(b) M+N(c) 2M+N(d) 2M-NThe question was asked in my homework.The question is from Main Memory Organisation topic in portion Processor & Memory of Computer Fundamentals

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The CORRECT option is (a) M*N

Explanation: Storage capacity is the product of a number of MEMORY locations that is the number of words and the word size or the number of bits stored per location. Storage capacity should be as LARGE as possible.

2.

What is the location of the internal registers of CPU?(a) Internal(b) On-chip(c) External(d) MotherboardI have been asked this question during an online exam.This interesting question is from Main Memory Organisation in division Processor & Memory of Computer Fundamentals

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The correct ANSWER is (b) On-chip

To elaborate: The INTERNAL REGISTERS are present on-chip. They are therefore present inside the CPU. L1 cache is ALSO present on-chip inside the CPU.

3.

MAR stands for ___________(a) Memory address register(b) Main address register(c) Main accessible register(d) Memory accessible registerI have been asked this question during an online exam.Query is from Main Memory Organisation in chapter Processor & Memory of Computer Fundamentals

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4.

____________ storage is a system where a robotic arm will connect or disconnect off-line mass storage media according to the computer operating system demands.(a) Secondary(b) Virtual(c) Tertiary(d) MagneticThis question was posed to me in my homework.The query is from Main Memory Organisation in section Processor & Memory of Computer Fundamentals

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The correct answer is (c) TERTIARY

Easy EXPLANATION: The tertiary storage is the correct OPTION. It is used in the realms of enterprise storage and SCIENTIFIC computing on large COMPUTER systems and business computer networks and is something a typical personal computer never sees firsthand.

5.

Which of the following is independent of the address bus?(a) Secondary memory(b) Main memory(c) Onboard memory(d) Cache memoryI have been asked this question at a job interview.The doubt is from Main Memory Organisation in chapter Processor & Memory of Computer Fundamentals

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Correct answer is (a) Secondary memory

Best explanation: The secondary memory is independent of the ADDRESS bus. It increases the STORAGE SPACE. It is implemented in the form of magnetic storage DEVICES.

6.

Size of the ________ memory mainly depends on the size of the address bus.(a) Main(b) Virtual(c) Secondary(d) CacheThe question was asked in an interview for internship.This is a very interesting question from Main Memory Organisation in portion Processor & Memory of Computer Fundamentals

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Correct ANSWER is (a) Main

Easiest explanation: The size of the main memory depends on the size of the address bus of the CPU. The main memory mainly consists of RAM and ROM, where RAM contains the CURRENT data and programs and ROM contains permanent programs LIKE BIOS.

7.

Any electronic holding place where data can be stored and retrieved later whenever required is ____________(a) memory(b) drive(c) disk(d) circuitThis question was posed to me in a national level competition.Question is taken from Main Memory Organisation in section Processor & Memory of Computer Fundamentals

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Right choice is (a) MEMORY

Easiest explanation: Memory is the place where data can be STORED and later RETRIEVED. Memory can be of classified into register, cache, main memory, ETC.

8.

The memory implemented using the semiconductor chips is _________(a) Cache(b) Main(c) Secondary(d) RegistersThe question was asked in an online quiz.This intriguing question comes from Main Memory Organisation topic in section Processor & Memory of Computer Fundamentals

Answer» RIGHT answer is (B) Main

Easy explanation: The main memory is IMPLEMENTED using semiconductor chips. Main memory is located on the motherboard. It mainly consists of RAM and small amount of ROM.
9.

Which of the following is the fastest means of memory access for CPU?(a) Registers(b) Cache(c) Main memory(d) Virtual MemoryThe question was posed to me in an interview for job.This is a very interesting question from Main Memory Organisation topic in division Processor & Memory of Computer Fundamentals

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The CORRECT choice is (a) Registers

Easy explanation: Registers are the FASTEST MEANS of access for CPU. Registers are the SMALL memory locations which are present closest to the CPU.

10.

Cache memory is the onboard storage.(a) True(b) FalseThis question was addressed to me in an interview.The doubt is from Main Memory Organisation in chapter Processor & Memory of Computer Fundamentals

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The correct answer is (a) True

Easiest explanation: CACHE Memory is the memory closest to the CPU. REGISTERS, Cache and the main memory are the means of onboard STORAGE in the COMPUTER system.

11.

A circuitry that processes that responds to and processes the basic instructions that are required to drive a computer system is ________(a) Memory(b) ALU(c) CU(d) ProcessorI got this question during a job interview.This interesting question is from Processor & Its Types in portion Processor & Memory of Computer Fundamentals

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The CORRECT ANSWER is (d) Processor

Easy explanation: The processor is responsible for processing the basic instructions in order to DRIVE a COMPUTER. The primary functions of a processor are fetch, decode and execute.

12.

MAR stands for ___________(a) Memory address register(b) Main address register(c) Main accessible register(d) Memory accessible registerThe question was posed to me by my school teacher while I was bunking the class.Asked question is from Processor & Its Types in division Processor & Memory of Computer Fundamentals

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Right choice is (a) Memory ADDRESS register

Easy explanation: The MAR STANDS for memory address register. It holds the address of the ACTIVE memory location.

13.

The architecture that uses a tighter coupling between the compiler and the processor is ____________(a) EPIC(b) Multi-core(c) RISC(d) CISCThe question was posed to me in a job interview.This interesting question is from Processor & Its Types in section Processor & Memory of Computer Fundamentals

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Correct option is (a) EPIC

To explain I would say: EPIC STANDS for Explicitly parallel instruction computing. It has a tighter COUPLING between the compiler and the processor. It enables the compiler to extract maximum parallelism in the ORIGINAL code.

14.

Processor which is complex and expensive to produce is ________(a) RISC(b) EPIC(c) CISC(d) Multi-coreI have been asked this question in an interview for job.Question is taken from Processor & Its Types topic in chapter Processor & Memory of Computer Fundamentals

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The correct choice is (C) CISC

The explanation: CISC stands for complex INSTRUCTION SET computer. It is mostly USED in personal computers. It has a LARGE instruction set and a variable length of instructions.

15.

Which of the following processor has a fixed length of instructions?(a) CISC(b) RISC(c) EPIC(d) Multi-coreI had been asked this question in a national level competition.Question is taken from Processor & Its Types in portion Processor & Memory of Computer Fundamentals

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16.

CISC stands for____________(a) Complex Information Sensed CPU(b) Complex Instruction Set Computer(c) Complex Intelligence Sensed CPU(d) Complex Instruction Set CPUI had been asked this question during an interview.Enquiry is from Processor & Its Types topic in section Processor & Memory of Computer Fundamentals

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Correct answer is (b) COMPLEX Instruction SET Computer

The best explanation: CISC is a large instruction set computer. It has VARIABLE LENGTH instructions. It also has variety of addressing MODES.

17.

It takes one clock cycle to perform a basic operation.(a) True(b) FalseThis question was posed to me in semester exam.I'd like to ask this question from Processor & Its Types in section Processor & Memory of Computer Fundamentals

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Right option is (a) True

The explanation: It takes exactly one clock cycle to PERFORM a BASIC operation, such as moving a byte of MEMORY from a LOCATION to another location in the COMPUTER.

18.

The number of clock cycles per second is referred as________(a) Clock speed(b) Clock frequency(c) Clock rate(d) Clock timingI had been asked this question in quiz.Query is from Processor & Its Types topic in section Processor & Memory of Computer Fundamentals

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Correct answer is (a) CLOCK speed

For EXPLANATION I would say: The number of clock CYCLES PER second is the clock speed. It is generally MEASURED in gigahertz(10^9 cycles/sec) or megahertz (10^6 cycles/sec).

19.

The operation that does not involves clock cycles is _________(a) Installation of a device(b) Execute(c) Fetch(d) DecodeI got this question at a job interview.My question is from Processor & Its Types topic in chapter Processor & Memory of Computer Fundamentals

Answer» CORRECT ANSWER is (a) INSTALLATION of a device

The explanation is: Normally, several clock cycles are required to fetch, execute and decode a PARTICULAR program.

Installation of a device is done by the system on its own.
20.

The transfer between CPU and Cache is______________(a) Block transfer(b) Word transfer(c) Set transfer(d) Associative transferThe question was posed to me in quiz.This interesting question is from Cache Memory topic in chapter Processor & Memory of Computer Fundamentals

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The CORRECT answer is (b) Word transfer

Best explanation: The transfer is a word transfer. In the MEMORY subsystem, word is transferred over the memory DATA bus and it TYPICALLY has a width of a word or half-word.

21.

Computer has a built-in system clock that emits millions of regularly spaced electric pulses per _____ called clock cycles.(a) second(b) millisecond(c) microsecond(d) minuteI got this question by my school principal while I was bunking the class.This key question is from Processor & Its Types topic in section Processor & Memory of Computer Fundamentals

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22.

The number of sign bits in a 32-bit IEEE format is ____(a) 1(b) 11(c) 9(d) 23The question was asked in a job interview.Enquiry is from Cache Memory topic in section Processor & Memory of Computer Fundamentals

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Right OPTION is (a) 1

The BEST I can explain: There is only 1 sign bit in all the STANDARDS. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.

23.

In ____________ mapping, the data can be mapped anywhere in the Cache Memory.(a) Associative(b) Direct(c) Set Associative(d) IndirectThis question was addressed to me in an internship interview.My question comes from Cache Memory in chapter Processor & Memory of Computer Fundamentals

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Correct ANSWER is (a) Associative

Explanation: This happens in the associative mapping. In this CASE, a block of data from the main memory can be MAPPED ANYWHERE in the CACHE memory.

24.

Which of the following is an efficient method of cache updating?(a) Snoopy writes(b) Write through(c) Write within(d) Buffered writeThe question was asked in examination.I'd like to ask this question from Cache Memory in section Processor & Memory of Computer Fundamentals

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Right answer is (a) Snoopy writes

To EXPLAIN: Snoopy writes is the efficient METHOD for updating the cache. In this CASE, the cache controller snoops or monitors the OPERATIONS of other bus MASTERS.

25.

Which of the following is not a write policy to avoid Cache Coherence?(a) Write through(b) Write within(c) Write back(d) Buffered writeI had been asked this question by my school principal while I was bunking the class.My question is from Cache Memory topic in chapter Processor & Memory of Computer Fundamentals

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Correct ANSWER is (B) WRITE within

The explanation: There is no policy which is CALLED as the write within policy. The other three options are the write policies which are used to avoid cache COHERENCE.

26.

When the data at a location in cache is different from the data located in the main memory, the cache is called _____________(a) Unique(b) Inconsistent(c) Variable(d) FaultThe question was asked in exam.This intriguing question originated from Cache Memory topic in division Processor & Memory of Computer Fundamentals

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The CORRECT option is (b) Inconsistent

The EXPLANATION: The cache is said to be inconsistent. Inconsistency must be AVOIDED as it leads to serious data BUGS.

27.

LRU stands for ___________(a) Low Rate Usage(b) Least Rate Usage(c) Least Recently Used(d) Low Required UsageThis question was posed to me in my homework.I need to ask this question from Cache Memory topic in division Processor & Memory of Computer Fundamentals

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The correct OPTION is (c) LEAST Recently USED

To explain I would SAY: LRU stands for Least Recently Used. LRU is a type of REPLACEMENT policy used by the cache memory.

28.

Whenever the data is found in the cache memory it is called as_________(a) HIT(b) MISS(c) FOUND(d) ERRORThis question was addressed to me in an online quiz.I'd like to ask this question from Cache Memory in section Processor & Memory of Computer Fundamentals

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Correct answer is (a) HIT

The BEST explanation: Whenever the data is found in the CACHE memory, it is CALLED as Cache HIT. CPU first CHECKS in the cache memory SINCE it is closest to the CPU.

29.

What is the high speed memory between the main memory and the CPU called?(a) Register Memory(b) Cache Memory(c) Storage Memory(d) Virtual MemoryI had been asked this question during an online exam.I'm obligated to ask this question of Cache Memory in portion Processor & Memory of Computer Fundamentals

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Correct option is (B) CACHE MEMORY

The EXPLANATION is: It is called the Cache Memory. The cache memory is the high speed memory between the main memory and the CPU.

30.

Cache Memory is implemented using the DRAM chips.(a) True(b) FalseThe question was asked in exam.I would like to ask this question from Cache Memory in division Processor & Memory of Computer Fundamentals

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The correct answer is (b) False

The explanation: The CACHE MEMORY is IMPLEMENTED USING the SRAM chips and not the DRAM chips. SRAM stands for Static RAM. It is faster and is expensive.

31.

New CPU whose instruction set includes the instruction set of its predecessor CPU is said to be ___________ with its predecessor.(a) fully compatible(b) forward compatible(c) compatible(d) backward compatibleThe question was posed to me during an online exam.This intriguing question originated from Registers topic in section Processor & Memory of Computer Fundamentals

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The correct answer is (d) BACKWARD compatible

For explanation: The CPU is CALLED backward compatible since it contains the INSTRUCTION set of its PREDECESSOR. Manufacturers tend to group their CPUs into families having similar instruction set.

32.

The number of sign bits in a 32-bit IEEE format__________(a) 1(b) 11(c) 9(d) 23I had been asked this question in semester exam.The question is from Registers in section Processor & Memory of Computer Fundamentals

Answer» RIGHT option is (a) 1

For EXPLANATION: There is only 1 sign bit in all the standards. In a 32-bit FORMAT, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.
33.

What kind of a flag is the sign flag?(a) General Purpose(b) Status(c) Address(d) InstructionI had been asked this question in an online quiz.The doubt is from Registers topic in section Processor & Memory of Computer Fundamentals

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Right CHOICE is (b) Status

For EXPLANATION: Sign flag is a TYPE of status REGISTER or the flag register. It is used to indicate the sign of CERTAIN bits.

34.

What is correct instruction if you want the control to go to the location 2000h?(a) MOV 2000h(b) MOV A, 2000h(c) JMP 2000h(d) RET 2000hI have been asked this question in an interview for job.This is a very interesting question from Registers topic in division Processor & Memory of Computer Fundamentals

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The correct answer is (c) JMP 2000h

To EXPLAIN I would SAY: The JMP INSTRUCTION is USED to move to a particular location. In 8085 microprocessor, JMP statement tells the processor to go to location 2000h (here).

35.

Which of the following is a data transfer instruction?(a) STA 16-bit address(b) ADD A, B(c) MUL C, D(d) RETThis question was posed to me during an interview.This interesting question is from Registers topic in division Processor & Memory of Computer Fundamentals

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The correct ANSWER is (a) STA 16-bit ADDRESS

To explain I would SAY: The instruction STA 16-bit address is a data transfer instruction.

STA MEANS Store in Accumulator.

36.

Which of the following is not a visible register?(a) General Purpose Registers(b) Address Register(c) Status Register(d) MARI have been asked this question in exam.Origin of the question is Registers topic in section Processor & Memory of Computer Fundamentals

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The CORRECT OPTION is (d) MAR

The explanation is: MAR or the memory address register is not a visible register. This register is USER inaccessible. It contains the address of the memory block to be read or written to.

37.

The _________ holds the contents of the accessed memory word.(a) MAR(b) MBR(c) PC(d) IRI have been asked this question in my homework.Asked question is from Registers topic in portion Processor & Memory of Computer Fundamentals

Answer» CORRECT choice is (B) MBR

To elaborate: The MBR HOLDS the contents of the accessed (read/written) MEMORY word.

MBR stands for Memory Buffer Register.
38.

The length of a register is called _______(a) word limit(b) word size(c) register limit(d) register sizeI had been asked this question in an online interview.The question is from Registers topic in section Processor & Memory of Computer Fundamentals

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The correct ANSWER is (B) word size

Best EXPLANATION: The length of a register is called word size.It tells the number of bits a register can store.

Registers are a PART of the CPU.

39.

Opcode indicates the operations to be performed.(a) True(b) FalseI have been asked this question during an online exam.My enquiry is from Registers topic in division Processor & Memory of Computer Fundamentals

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Right choice is (a) True

Easiest EXPLANATION: Every INSTRUCTION has an opcode.Additionally, it may have ONE or more operands and the OP code indicates the operation to be PERFORMED.

40.

CPU has built-in ability to execute a particular set of machine instructions, called as __________(a) Instruction Set(b) Registers(c) Sequence Set(d) User instructionsThis question was posed to me during an online exam.The doubt is from Registers topic in section Processor & Memory of Computer Fundamentals

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Right ANSWER is (a) Instruction SET

Explanation: An instruction is any task which is to be PERFORMED by the PROCESSOR. Instructions are stored in the register. Instruction set is the set of MACHINE instructions.

41.

What does D in the D-flip flop stand for?(a) Digital(b) Direct(c) Delay(d) DurableThe question was asked in homework.This question is from CPU & Control Unit in chapter Processor & Memory of Computer Fundamentals

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Correct OPTION is (c) DELAY

The best explanation: In the hardwired control unit, the delay ELEMENT method uses D-flip flop which causes a delay. Since, in the delay element method, there must be a FINITE time gap between the 2 steps.

42.

The functions of execution and sequencing are performed by using______________(a) Input Signals(b) Output Signals(c) Control Signals(d) CPUThe question was posed to me in a job interview.My question comes from CPU & Control Unit in portion Processor & Memory of Computer Fundamentals

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Correct ANSWER is (C) Control Signals

Easy explanation: Sequencing followed by the process of execution is PERFORMED by the Control signals. Sequencing is traversing each and every operation whereas execution causes the PERFORMANCE of each operation.

43.

Causing the CPU to step through a series of micro operations is called _________(a) Execution(b) Runtime(c) Sequencing(d) PipeliningI had been asked this question in an international level competition.This interesting question is from CPU & Control Unit topic in chapter Processor & Memory of Computer Fundamentals

Answer» RIGHT CHOICE is (c) Sequencing

Easiest EXPLANATION: Sequencing is the process of causing the CPU to step through a series of micro operations. EXECUTION causes the performance of each micro OPERATION.
44.

The portion of the processor which contains the hardware required to fetch the operations is _______(a) Datapath(b) Processor(c) Control(d) Output unitI had been asked this question by my college professor while I was bunking the class.My question is based upon CPU & Control Unit in division Processor & Memory of Computer Fundamentals

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Correct option is (a) Datapath

For explanation I would say: The datapath contains the HARDWARE required to fetch the operations. The CONTROL tells the DATA path what needs to be DONE.

45.

Which of the following holds the last instruction fetched?(a) PC(b) MAR(c) MBR(d) IRI had been asked this question in an interview for internship.I want to ask this question from CPU & Control Unit in chapter Processor & Memory of Computer Fundamentals

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Correct OPTION is (d) IR

To elaborate: The IR which stands for the instruction register CONTAINS the last instruction fetched.

All the OTHERS OPTIONS are registers which are used for the fetch operation.

46.

What does PC stand for?(a) Program Changer(b) Program Counter(c) Performance Counter(d) Performance ChangerI had been asked this question in class test.This interesting question is from CPU & Control Unit in portion Processor & Memory of Computer Fundamentals

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Correct answer is (b) Program COUNTER

Easiest explanation: The Program counter contains the address of the next instruction which is to be FETCHED by the control unit.

All other OPTIONS are INVALID.

47.

In the instruction ADD A, B, the answer gets stored in___________(a) B(b) A(c) Buffer(d) CI have been asked this question in homework.The above asked question is from CPU & Control Unit in division Processor & Memory of Computer Fundamentals

Answer» CORRECT choice is (b) A

The best explanation: In any instruction of the form ADD A, B; the answer GETS STORED in the A REGISTER. The FORMAT is: ADD Destination, Source.
48.

What does MBR stand for?(a) Main Buffer Register(b) Memory Buffer Routine(c) Main Buffer Routine(d) Memory Buffer RegisterI had been asked this question during an internship interview.My doubt is from CPU & Control Unit in chapter Processor & Memory of Computer Fundamentals

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The correct CHOICE is (d) MEMORY Buffer Register

The best explanation: The binary subtraction 0 – 1 GIVES the result 1.

A borrow of 1 is although generated and is REMOVED from the NEXT higher column.

49.

Control Unit acts as the central nervous system of the computer.(a) True(b) FalseI had been asked this question during an online exam.My query is from CPU & Control Unit in division Processor & Memory of Computer Fundamentals

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Correct choice is (a) True

To EXPLAIN I would SAY: The control unit is referred to as the CENTRAL nervous system because it selects and interprets the instructions and COORDINATES execution.

50.

Brain of computer is____________(a) Control unit(b) Arithmetic and Logic unit(c) Central Processing Unit(d) MemoryThe question was posed to me in my homework.My doubt is from CPU & Control Unit in portion Processor & Memory of Computer Fundamentals

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Right CHOICE is (C) Central Processing Unit

To explain: The CPU is REFERRED to as the brain of a computer.

It CONSISTS of a control unit and the arithmetic and logic unit. It is responsible for performing all the processes and operations.