Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz

1.	Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is
Answer» 3.2Explanation:SPEEDUP = ExecutionTimeOld / ExecutionTimeNewExecutionTimeOld = CPIOld * CycleTimeOld [Here CPI is Cycles Per Instruction] = CPIOld * CycleTimeOld = 4 * 1/2.5 NANOSECONDS = 1.6 nsSince there are no STALLS, CPUnew can be assumed 1 on average.ExecutionTimeNew = CPInew * CycleTimenew = 1 * 1/2 = 0.5Speedup = 1.6 / 0.5 = 3.2