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(D) Plise difference (3) between input and output voltage for the following circuits () and (Gi)10.0. The phase differenキVoR.will be(A) 0 and 0(C) π/2 and π/2(B)(D)π/2 and 0< δ π/2 respectively0 and 0 < δ π/2 respectively |
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Answer» As, we know that in capacitive circuit, the output voltage lags behind input by tan inverse of( R/Xc). So option B is correct |
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