InterviewSolution
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InterviewSolution
| 1. |
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB), The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.The number of clock cycles required for completion of execution of the sequence of instruction is ______ .Note – This was Numerical Type question.(A) 219(B) 104(C) 115(D) 220 |
| Answer» None | |