what are the control and status signals asserted by 8085 to enable the

1.	what are the control and status signals asserted by 8085 to enable the memory buffer in opcode fetch?
Answer» answer:- There are four main control and status signals. These are: address latch enable. This signal is a pulse that become 1 when the AD0-AD7 LINES have an address on them it becomes 0 after that this signal can be used to enable a latch to save the address bit from the AD lines. RD:Read.Active law indicate that the data must be read from the selected memory location or I/O port via data bus. WR: Write.Active law indicate that the data must be return into to the selected memory location aur or I/O port via data bus. IO/M- this signal SPECIFY whether the operation is memory operation (IO/M=0) this signal specify whether the operation is memory operation (IO/M=0)or an I/o=operation (lO/1=1) SI & S0- status signal to specify the kind of operation wing PERFORMANCE usually and use in small system. thankyou I hope you have satisfied please follow me .

what are the control and status signals asserted by 8085 to enable the memory buffer in opcode fetch?

Answer»

answer:-

There are four main control and status signals. These are:

address latch enable. This signal is a pulse that become 1 when the AD0-AD7 LINES have an address on them it becomes 0 after that this signal can be used to enable a latch to save the address bit from the AD lines.

RD:Read.Active law indicate that the data must be read from the selected memory location or I/O port via data bus.

WR: Write.Active law indicate that the data must be return into to the selected memory location aur or I/O port via data bus.

IO/M- this signal SPECIFY whether the operation is memory operation (IO/M=0)

this signal specify whether the operation is memory operation (IO/M=0)or an I/o=operation (lO/1=1)

SI & S0- status signal to specify the kind of operation wing PERFORMANCE usually and use in small system.

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