What Are The Different Design Constraints Occur In The Synthesis Phas

1.	What Are The Different Design Constraints Occur In The Synthesis Phase?
Answer» The steps that are involved in which the design constraint OCCURS are: first the creation of the clock with the frequency and the duty cycle gets CREATED. This clock helps in maintaining the flow and synchronizing various devices that are used. Define the transition TIME according the requirement on the input ports. The LOAD values are specified for the output ports that are mapped with the input ports. Setting of the delay values for both the input and output ports. The delay INCLUDES the input and output delay. Specify the case-settings to report the correct time that are matched with the specific paths. The clock uncertainty values are setup and hold to show the violations that are occurring. The steps that are involved in which the design constraint occurs are:

What Are The Different Design Constraints Occur In The Synthesis Phase?

Answer»

The steps that are involved in which the design constraint OCCURS are:

first the creation of the clock with the frequency and the duty cycle gets CREATED. This clock helps in maintaining the flow and synchronizing various devices that are used.
Define the transition TIME according the requirement on the input ports.
The LOAD values are specified for the output ports that are mapped with the input ports.
Setting of the delay values for both the input and output ports. The delay INCLUDES the input and output delay.
Specify the case-settings to report the correct time that are matched with the specific paths.
The clock uncertainty values are setup and hold to show the violations that are occurring.

The steps that are involved in which the design constraint occurs are: