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LOCAL SKEW : The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path.

Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain.

Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting SETUP requirement with in the LAUNCH and capture timing path. But the hold-requirement has to be met for the DESIGN.

Local skew : The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path.

Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain.

Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.

Latches are level-sensitive and flip-flops are EDGE sensitive. LATCH based design and flop based design is that latch allowes time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite COMPLEX.

Latches are level-sensitive and flip-flops are edge sensitive. latch based design and flop based design is that latch allowes time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex.

Tie-HIGH and Tie-Low cells are used to connect the gate of the TRANSISTOR to either power or ground. In DEEP sub micron processes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are PART of standard-cell library. The cells which REQUIRE Vdd, comes and connect to Tie high...(so tie high is a power supply cell)...while the cells which wants Vss connects itself to Tie-low.

Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In deep sub micron processes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high...(so tie high is a power supply cell)...while the cells which wants Vss connects itself to Tie-low.

While writing RTL(Register Transfer language),say in verilog or in VHDL language, we dont write the same module functionality again and again, we use a concept called as instantiation, where in as per the language, the instanciation of a module will behave like the parent module in terms of functionality, where during synthesis stage we need the full code so that the synthesis tool can STUDY the logic , structure and map it to the LIBRARY cells, so we use a command in synthesis , called as "UNIQUIFY" which will REPLACE the instantiations with the real logic, because once we are in a synthesis stages we have to visualize as real cells and no more modelling just for functionality ALONE, we need to visualize in-terms of PHYSICAL world as well. 

While writing RTL(Register Transfer language),say in verilog or in VHDL language, we dont write the same module functionality again and again, we use a concept called as instantiation, where in as per the language, the instanciation of a module will behave like the parent module in terms of functionality, where during synthesis stage we need the full code so that the synthesis tool can study the logic , structure and map it to the library cells, so we use a command in synthesis , called as "UNIQUIFY" which will replace the instantiations with the real logic, because once we are in a synthesis stages we have to visualize as real cells and no more modelling just for functionality alone, we need to visualize in-terms of physical world as well. 

There are different classification in which the timing control data is DIVIDED and they are:

1. Delay BASED timing control: this is based on timing control that allows to manage the component such that the delay can be notified and wherever it is required it can be given. The delays that are based on this are as:
   
   - Regular delay control: that controls the delay on the regular basis.
   - Intra-assignment delay control: that controls the internal delays.
   - Zero delay control
   
   
2. Events based timing control: this is based on the events that are performed when an event happens or a TRIGGER is set on an event that takes place. It includes
   
   - Regular event control
   - Named event control
   - Event OR control
   
   
3. Level sensitive timing control: this is based on the levels that are given LIKE 0 level or 1 level that is being given or shown and the data is being modified according the levels that are being set. When a level changes the timing control also changes.

There are different classification in which the timing control data is divided and they are:

• CMOS technology allows the power dissipation to be low and it gives more power output, whereas bipolar TAKES lots of power to run the system and the ciricutary require lots of power to GET activated.
• CMOS technology provides high input impedance that is low drive CURRENT that allow more current to be flown in the cirucit and keep the circuit in a good position, whereas it provides high drive current means more input impedance.
• CMOS technology provides scalable threshold voltage more in comparison to the Bipolar technology that provides low threshold voltage.
• CMOS technology provides high noise margin, PACKING density whereas Bipolory technology allows to have low noise margin so that to reduce the high volues and give low packing density of the components.

• PMOS consists of metal oxide semiconductor that is made on the n-type substrates and consists of active careers named as holes. These holes are used for migration purpose of the CHARGES between the p-type and the drain. Whereas, NMOS consists of the metal oxide semiconductor and they are made on p-type substrates. It consists of electrons as their carriers and migration happens between the n-type source and drain.
• On applying the HIGH voltage on the logic gates NMOS will be conducted and will get activated, whereas PMOS require low voltage to be activated.
• NMOS are faster than PMOS as the carriers that NMOS USES are electrons that TRAVELS faster than holes. The SPEED is twice as fast as holes.
• PMOS are more immune to noice than NMOS.

Depletion modes are used in MOSFET it is a device that remains ON at zero gate-source voltage. This device consists of load resistors that are used in the LOGIC circuits. This types are used in N-type depletion-load DEVICES that allow the threshold voltages to be taken and use of -3 V to +3V is done.

The drain is more positive in this comparison of PMOS where the polarities gets reversed. The MODE is usually determined by the SIGN of threshold voltage for N-type channel. Depletion mode is the positive one and used in many technologies to represent the actual logic circuit. It defines the logic family that is dependent on the silicon VLSI. This consists of pull-down switches and loads for pull-ups.

Depletion modes are used in MOSFET it is a device that remains ON at zero gate-source voltage. This device consists of load resistors that are used in the logic circuits. This types are used in N-type depletion-load devices that allow the threshold voltages to be taken and use of -3 V to +3V is done.

The drain is more positive in this comparison of PMOS where the polarities gets reversed. The mode is usually determined by the sign of threshold voltage for N-type channel. Depletion mode is the positive one and used in many technologies to represent the actual logic circuit. It defines the logic family that is dependent on the silicon VLSI. This consists of pull-down switches and loads for pull-ups.

The enhancement mode transistors are ALSO called as field effect transistors as they rely on the electric filed to control the shape and conductivity of the channel. This consists of one TYPE of charge CARRIER in a semiconductor material environment. This also uses the unipolar transistors to DIFFERENTIATE themselves with the single-carrier type operation transistors that consists of the bipolar junction transistor.

The uses of field effect transistor is to physical implementation of the semiconductor materials that is compared with the bipolar transistors. It PROVIDES with the majority of the charge carrier devices. The devices that consists of active channels to make the charge carriers pass through. It consists of the concept of drain and the source.

The enhancement mode transistors are also called as field effect transistors as they rely on the electric filed to control the shape and conductivity of the channel. This consists of one type of charge carrier in a semiconductor material environment. This also uses the unipolar transistors to differentiate themselves with the single-carrier type operation transistors that consists of the bipolar junction transistor.

The uses of field effect transistor is to physical implementation of the semiconductor materials that is compared with the bipolar transistors. It provides with the majority of the charge carrier devices. The devices that consists of active channels to make the charge carriers pass through. It consists of the concept of drain and the source.

• To make the design for an optimal pad ring there is a requirement for the corner-PADS that comes across all the corners of the pad-ring. It is used to give power continuity and keep the resistance low.
• It requires the pad ring that is to fulfil the power domains that is common for all the ground across all the domains.
• It requires the pad ring to contain simultaneous SWITCHING NOISE system that place the transfer cell pads in cross power domains for different pad length.
• Drive STRENGTH is been seen to check the current requirements and the timings to make the power pads.
• Choose a no-connection pad that is used to fill the pad-frame when there is no requirement for the inputs to be given. This consumes less power when there is no input given at a particular time.
• Checking of the oscillators pads take place that uses the synchronous circuits to make the clock DATA synchronize with the existing one.

The optimization technique that is used makes it difficult for the chain ordering system to route due to the congestion caused by the placement of the CELLS. There are tool available that automate the reordering of the chain to reduce the congestion that is produced at the first stage. It increases the problem of the chain system and this also ALLOW the overcoming of the buffers that have to be inserted into the scan PATH.

The increase of the hold time in the chain reordering can CAUSE great amount of delay. Chain reordering allows the cell to be come in the ordered format while using the DIFFERENT clock domains. It is used to reduce the time delay caused by random generation of the element and the placement of it.

The optimization technique that is used makes it difficult for the chain ordering system to route due to the congestion caused by the placement of the cells. There are tool available that automate the reordering of the chain to reduce the congestion that is produced at the first stage. It increases the problem of the chain system and this also allow the overcoming of the buffers that have to be inserted into the scan path.

The increase of the hold time in the chain reordering can cause great amount of delay. Chain reordering allows the cell to be come in the ordered format while using the different clock domains. It is used to reduce the time delay caused by random generation of the element and the placement of it.

To make a comparator there is a REQUIREMENT to use multiplexer that is having one input and many OUTPUTS. This allows the choosing of the maximum numbers that are required to design the comparator. The implementation of the 2 bit comparator can be done using the law of tigotomy that states that A > B, A < B, A = B (Law of trigotomy). The comparator can be implemented using:

combinational logic circuits or MULTIPLEXERS that uses the HDL language to write the schematic at RTL and gate level.

Behavioral model of comparator represented like:

MODULE comp0 (Y1,y2,y3,a,b);
input [1:0] a,b;
output y1,y2,y3;
wire y1,y2,y3;
assign y1= (a >b)? 1:0;
assign y2= (b >a)? 1:0;
assign y3= (a==b)? 1:0;
endmodule

To make a comparator there is a requirement to use multiplexer that is having one input and many outputs. This allows the choosing of the maximum numbers that are required to design the comparator. The implementation of the 2 bit comparator can be done using the law of tigotomy that states that A > B, A < B, A = B (Law of trigotomy). The comparator can be implemented using:

combinational logic circuits or multiplexers that uses the HDL language to write the schematic at RTL and gate level.

Behavioral model of comparator represented like:

module comp0 (y1,y2,y3,a,b);
input [1:0] a,b;
output y1,y2,y3;
wire y1,y2,y3;
assign y1= (a >b)? 1:0;
assign y2= (b >a)? 1:0;
assign y3= (a==b)? 1:0;
endmodule

The different design techniques to create the Layout for digital circuits are as follows:

• Digital design consists of the standard cells and represent the HEIGHT that is REQUIRED for the layout. The layout depends on the size of the transistor. It also consists of the specification for Vdd and GND metal PATHS that has to be maintained uniformly.
• Use of metal in one direction only to APPLY the metal directly. The metal can be used and displayed in any direction.
• Placing of the substrate that PLACE where it shows all the empty spaces of the layout where there is resistances.
• Use of fingered transistors allows the design to be more easy and it is easy to maintain a symmetry as well.

The different design techniques to create the Layout for digital circuits are as follows:

• Synchronous reset is the logic that will synthesize to smaller flip-flops. In this the CLOCK works as a filter providing the small reset glitches but the glitches occur on the active clock edge, whereas the ASYNCHRONOUS reset is ALSO known as reset release or reset removal. The designer is responsible of added the reset to the data paths.
• The synchronous reset is used for all the types of design that are used to filter the logic glitches provided between the clocks. Whereas, the CIRCUIT can be reset with or without the clock present.
• Synchronous reset doesn't allow the synthesis tool to be used easily and it distinguishes the reset signal from other data signal. The release of the reset can occur only when the clock is having its initial period. If the release happens near the clock edge then the flip-flops can be METASTABLE.

• Moore model consists of the MACHINE that have an entry action and the output depends only on the state of the machine, whereas mealy model only uses Input Actions and the output depends on the state and also on the previous inputs that are provided during the PROGRAM.
• Moore models are used to design the hardware systems, whereas both hardware and software systems can be designed using the mealy model.
• Mealy machine's output depend on the state and input, whereas the output of the moore machine depends only on the state as the program is written in the state only.
• Mealy machine is having the output by the combination of both input and the state and the change the state of state variables also have some delay when the change in the signal TAKES place, whereas in Moore machine doesn't have GLITCHES and its ouput is dependent only on states not on the input signal LEVEL.

To achieve better yeild then there should be reduction in maufacturability flaws. The circuit perfomance has to be high that REDUCES the parametric yield. This reduction is due to process variations The measures that can be taken are:

• CREATION of powerful runset files that consists of spacing and shorting rules. This also consists of all the permissions that has to be given to the user.
• Check the areas where the design is having LITHOGRAPHIC issues, that consists of sharp cuts.
• Use of redundant vias to reduce the BREAKAGE of the current and the barrier.
• Optimal placing of the de-coupling capacitances can be done so that there is a reduction in power-surges.

To achieve better yeild then there should be reduction in maufacturability flaws. The circuit perfomance has to be high that reduces the parametric yield. This reduction is due to process variations The measures that can be taken are:

To meet the design power TARGET there should be a process to design with Multi-VDD designs, this area requires high performance, and also the high VDD that requires low-performance. This is USED to create the voltage group that allow the appropriate level-shifter to shift and placed in cross-voltage DOMAINS. There is a design with the MULTIPLE threshold voltages that require high performance when the Vt becomes low.

This have lots of current leakage that makes the Vt cell to lower the performance. The reduction can be performed in the leakage power as the clock in this consume more power, so placing of an optimal clock controls the module and allow it to be given more power. Clock tree allow the SWITCHING to take place when the clock buffers are used by the clock gating cells and reduce the switching by the power reduction.

To meet the design power target there should be a process to design with Multi-VDD designs, this area requires high performance, and also the high VDD that requires low-performance. This is used to create the voltage group that allow the appropriate level-shifter to shift and placed in cross-voltage domains. There is a design with the multiple threshold voltages that require high performance when the Vt becomes low.

This have lots of current leakage that makes the Vt cell to lower the performance. The reduction can be performed in the leakage power as the clock in this consume more power, so placing of an optimal clock controls the module and allow it to be given more power. Clock tree allow the switching to take place when the clock buffers are used by the clock gating cells and reduce the switching by the power reduction.

There are three types of skew that are used in VLSI. The skew are used in clock to reduce the delay or to understand the process accordingly. The skew are as FOLLOWS:

Local skew: This contain the difference between the launching flip-flop and the destination flip-flop. This defines a time path between the two.

Global skew: Defines the difference between the earliest COMPONENT reaching the flip flow and the the latest arriving at the flip flow with the same clock domain. In this delays are not measured and the clock is provided the same.

Useful skew: Defines the delay in capturing a flip flop paths that helps in setting up the environment with SPECIFIC REQUIREMENT for the launch and capture of the timing path. The hold requirement in this CASE has to be met for the design purpose.

There are three types of skew that are used in VLSI. The skew are used in clock to reduce the delay or to understand the process accordingly. The skew are as follows:

Local skew: This contain the difference between the launching flip-flop and the destination flip-flop. This defines a time path between the two.

Global skew: Defines the difference between the earliest component reaching the flip flow and the the latest arriving at the flip flow with the same clock domain. In this delays are not measured and the clock is provided the same.

Useful skew: Defines the delay in capturing a flip flop paths that helps in setting up the environment with specific requirement for the launch and capture of the timing path. The hold requirement in this case has to be met for the design purpose.

The steps that are involved in which the design constraint OCCURS are:

1. first the creation of the clock with the frequency and the duty cycle gets CREATED. This clock helps in maintaining the flow and synchronizing various devices that are used.
2. Define the transition TIME according the requirement on the input ports.
3. The LOAD values are specified for the output ports that are mapped with the input ports.
4. Setting of the delay values for both the input and output ports. The delay INCLUDES the input and output delay.
5. Specify the case-settings to report the correct time that are matched with the specific paths.
6. The clock uncertainty values are setup and hold to show the violations that are occurring.

The steps that are involved in which the design constraint occurs are:

Metastability is the unknown state and it prevents the violations using the following steps:

1. proper synchronizers are used that can be two stage or three stage whenever the data comes from the asynchronous domain. This helps in recovering the metastable state event.
2. The synchronizers are used in between cross-clocking domains. This reduces the metastability by removing the delay that is caused by the data ELEMENT that are coming and TAKING time to get removed from the surface of metal.
3. Use of faster flip-flops that ALLOW the TRANSACTION to be more faster and it removes the delay time between the one component to another component. It uses a narrower metastable window that makes the delay happen but faster flip-flops help in making the process faster and REDUCE the time delay as well.

Metastability is the unknown state and it prevents the violations using the following steps:

Metastability is an unknown state that is given as neither one or zero. It is used in designing the SYSTEM that violates the setup or hole time REQUIREMENTS. The setup time requirement need the data to be stable before the clock-edge and the hold time requires the data to be stable after the clock edge has passed. There are potential violation that can lead to setup and hold violations as well. The data that is produced in this is totally asynchronous and clocked synchronous. This provide a way to setup the state through which it can be known that the violations that are OCCURING in the system and a PROPER design can be provided by the USE of several other functions.

Metastability is an unknown state that is given as neither one or zero. It is used in designing the system that violates the setup or hole time requirements. The setup time requirement need the data to be stable before the clock-edge and the hold time requires the data to be stable after the clock edge has passed. There are potential violation that can lead to setup and hold violations as well. The data that is produced in this is totally asynchronous and clocked synchronous. This provide a way to setup the state through which it can be known that the violations that are occuring in the system and a proper design can be provided by the use of several other functions.

Tie-high and tie-low are used to connect the transistors of the gate by using either the power or the ground. The gates are connected using the power or ground then it can be turned off and on due to the power bounce from the ground. The cells are used to STOP the bouncing and easy from of the current from one CELL to ANOTHER. These cells are required VDD that connects to the tie-high cell as there is a power supply that is high and tie-low gets connected to Vss. This connection gets ESTABLISHED and the transistors function properly without the need of any ground bounce occurring in any cell.

Tie-high and tie-low are used to connect the transistors of the gate by using either the power or the ground. The gates are connected using the power or ground then it can be turned off and on due to the power bounce from the ground. The cells are used to stop the bouncing and easy from of the current from one cell to another. These cells are required Vdd that connects to the tie-high cell as there is a power supply that is high and tie-low gets connected to Vss. This connection gets established and the transistors function properly without the need of any ground bounce occurring in any cell.

Antenna violation occurs during the process of PLASMA etching in which the CHARGES generating from one metal strip to another gets accumlated at a single place. The longer the strip the more the charges gets accumulated. The PREVENTION can be done by following method:

• CREATING a jogging the metal line, that consists of atleast one metal above the protected layer.
• There is a requirement to jog the metal that is above the metal getting the etching effect. This is due to the fact that if a metal gets the etching then the other metal gets disconnected if the prevention measures are not TAKEN.
• There is a way to prevent it by adding the reverse Diodes at the gates that are used in the circuits.

Antenna violation occurs during the process of plasma etching in which the charges generating from one metal strip to another gets accumlated at a single place. The longer the strip the more the charges gets accumulated. The prevention can be done by following method:

There are few steps that has to be performed to solved the SETUP and hold violations in VLSI. The steps are as follows:

• The optimization and RESTRUCTURING of the logic between the flops are carried WAY. This way the logics are combined and it helps in solving this PROBLEM.
• There is way to modify the flip-flops that offer lesser setup delay and provide faster services to setup a device. Modifying the launch-flop to have a better hold on the clock pin, which provides CK->Q that makes the launch-flop to be fast and helps in fixing the setup violations.
• The network of the clock can be modified to reduce the delay or slowing down of the clock that captures the action of the flip-flop.
• There can be added delay/buffer that allows less delay to the FUNCTION that is used.

There are few steps that has to be performed to solved the setup and hold violations in VLSI. The steps are as follows:

As discussed in the above QUESTION, the Vt DEPENDS on the VOLTAGE CONNECTED to the BODY terminal. It also depends on the temperature, the magnitude of Vt decreases by about 2mV for every 1oC rise in temperature.

As discussed in the above question, the Vt depends on the voltage connected to the Body terminal. It also depends on the temperature, the magnitude of Vt decreases by about 2mV for every 1oC rise in temperature.

When a POSITIVE voltage is applied across GATE, it causes the free holes (positive CHARGE) to be repelled from the region of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave BEHIND a carrier-depletion region.

When a positive voltage is applied across Gate, it causes the free holes (positive charge) to be repelled from the region of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave behind a carrier-depletion region.

Cut-off region: When VGS &LT; VT, no CHANNEL is induced and the MOSFET will be in cut-off region. No CURRENT flows.

Triode region: When VGS ≥ Vt, a channel will be induced and current starts flowing if VDS > 0. MOSFET will be in triode region as long as VDS < VGS - Vt.

Saturation region: When VGS ≥ Vt, and VDS ≥ VGS - Vt, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when VDS is further INCREASED.

Cut-off region: When VGS < Vt, no channel is induced and the MOSFET will be in cut-off region. No current flows.

Triode region: When VGS ≥ Vt, a channel will be induced and current starts flowing if VDS > 0. MOSFET will be in triode region as long as VDS < VGS - Vt.

Saturation region: When VGS ≥ Vt, and VDS ≥ VGS - Vt, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when VDS is further increased.

For a MOSFET when VGS is greater than Vt, a channel is INDUCED. As we increase VDS CURRENT starts flowing from Drain to Source (triode region). When we further increase VDS, till the voltage between gate and channel at the drain end to become Vt, i.e. VGS - VDS = Vt, the channel depth at Drain end decreases ALMOST to zero, and the channel is said to be PINCHED off. This is where a MOSFET enters saturation region.

For a MOSFET when VGS is greater than Vt, a channel is induced. As we increase VDS current starts flowing from Drain to Source (triode region). When we further increase VDS, till the voltage between gate and channel at the drain end to become Vt, i.e. VGS - VDS = Vt, the channel depth at Drain end decreases almost to zero, and the channel is said to be pinched off. This is where a MOSFET enters saturation region.

The value of voltage between Gate and SOURCE i.e. VGS at which a sufficient NUMBER of MOBILE electrons accumulate in the channel region to form a conducting channel is called threshold voltage (Vt is POSITIVE for NMOS and negative for PMOS).

The value of voltage between Gate and Source i.e. VGS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called threshold voltage (Vt is positive for NMOS and negative for PMOS).

MOSFET has THREE regions of operation: the cut-off REGION, the TRIODE region, and the saturation region.

The cut-off region and the triode region are used to operate as SWITCH. The saturation region is used to operate as amplifier.

MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.

The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier.

Compared to BJTs, MOSFETS can be made very small as they OCCUPY very small silicon area on IC chip and are relatively simple in TERMS of manufacturing. Moreover digital and memory ICs can be implemented with circuits that USE only MOSFETs i.e. no resistors, diodes, etc.

Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon area on IC chip and are relatively simple in terms of manufacturing. Moreover digital and memory ICs can be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.