What Is Synthesis?

1.	What Is Synthesis?
Answer» Synthesis is the stage in the design flow which is concerned with translating your Verilog CODE into gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually PRODUCE gates - it will OUTPUT a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA VENDOR. Synthesis is the stage in the design flow which is concerned with translating your Verilog code into gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

Answer»

Synthesis is the stage in the design flow which is concerned with translating your Verilog CODE into gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually PRODUCE gates - it will OUTPUT a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA VENDOR.

Synthesis is the stage in the design flow which is concerned with translating your Verilog code into gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

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