1.

When Are Dft And Formal Verification Used?

Answer»

DFT:

  • manufacturing defects like stuck at "0" or "1".
  • test for set of rules followed during the initial design stage.

FORMAL verification:

  • Verification of the operation of the design, i.e, to see if the design FOLLOWS spec.
  • gate NETLIST == RTL ?
  • using mathematics and STATISTICAL ANALYSIS to check for equivalence.

DFT:

Formal verification:



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