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Right option is (b) by data direction REGISTER

To elaborate: The implementation of parallel PORT uses a couple of BUFFERS which are enabled by the data direction register by setting the CORRESPONDING bit of the register.

The correct option is (d) 2D model

For EXPLANATION I would say: An address stride is specified which can be used for CALCULATING the OFFSET to the base address at the terminal of count. This address stride is used in the 2D model of the DMA CONTROLLER.

Right answer is (c) bus requester

The explanation is: The bus requester REQUESTS the bus from the main CPU. In EARLIER design, the processor bus does not support the multi master system and there were no bus REQUEST SIGNALS. In such cases, the processor clock was EXTENDED.

Correct answer is (b) hardware handshaking

Explanation: The FIRST FLOW control method is the hardware handshaking in which the hardware in the UART detects the POTENTIAL overrun and it will ASSERT a handshake line to tell the other UART to stop the transmission.

Correct choice is (b) extended address

To elaborate: For providing more ADDRESSING, an extended address is DEVELOPED which possesses two bytes in which the first byte uses a SPECIAL CODE to distinguish it from a single byte address so that the single byte and double byte address slaves can use a shared bus.

The correct answer is (b) telegram

Explanation: The data is transmitted in PACKETS with a having ONE or more BYTES. These packets of data are ALSO KNOWN as a telegram.

Correct OPTION is (a) MULTIFUNCTION I/O port

The explanation is: The multifunction I/O ports can be DESCRIBED as the general-purpose and it can be SHARED with other peripherals.

Right answer is (a) combined FORMAT

To explain I would say: Combined format is an EFFICIENT method for the EEPROM because it is having a LARGE NUMBER of REGISTERS.

The CORRECT answer is (c) Intel 8237

For EXPLANATION I would SAY: The Intel 8237 is the DMA used in the IBM PC. 8253, 8254 and 8259 are timers developed by Intel.

The correct answer is (C) ring indicator

The explanation is: The 22ND pin in DB-25 and the 9th pin in the DB-9 INDICATES a ring indicator which is asserted when a connected modem has DETECTED an INCOMING call.

The correct choice is (a) mode 5

The best EXPLANATION: The mode 5 or the hardware triggered strobe is similar to the mode 4 or the square wave RATE generator expect that the retriggering is done by the external gate pin.

Right choice is (b) 3

The BEST explanation: There are three classifications for the DMA controllers BASED on the ADDRESS CAPABILITY. These are 1D, 2D and 3D.

The correct OPTION is (a) universal asynchronous RECEIVER TRANSMITTER

Best explanation: The UART or universal asynchronous receiver transmitter is USED for the DATA transmission at a predefined speed or baud rate.

Right choice is (C) 2

Easy explanation: The serial INTERFACE is divided into TWO, physical interface and the ELECTRICAL interface.

Right option is (d) M-Bus

To ELABORATE: M-Bus or MOTOROLA Bus is an ideal INTERFACE for LCD controllers, A/D converters, EEPROMs and many other components which can benefit faster TRANSMISSION.

Right option is (c) 2

For explanation I WOULD say: The basic operation of the PARALLEL port dealt with two types of REGISTERS which are called data DIRECTION register and the data register.

Correct CHOICE is (b) serial peripheral INTERFACE

For explanation: The serial parallel interface BUS is a commonly used interface which involves master SLAVE mechanism. The shift registers are worked as master and the slave devices are driven by a COMMON clock.

Correct CHOICE is (d) MC68HC11

The best explanation: The MC68HC05 and MC68HC11 microcontrollers use the serial PERIPHERAL interface for the peripheral interfacing.

Right option is (b) bidirectional port

Explanation: By using the bidirectional ports, each master can monitor the line and CONFIRM its expected STATE and if it is not matched, a MISMATCH or COLLISION had occurred which will discontinue the transmission by the master.

Right answer is (a) OUT pin

Easy explanation: The Intel 8253 TIMER has no interrupt PINS. THEREFORE, the timer OUT pin is USED to GENERATE an external interrupt signal.

The correct option is (b) INTEL 8253

To explain: The Intel 8253 timer is suitable for the IBM PC. IA-32 and Intel 64 are the offload timers USED only for Intel. The 8051 timer is used for the timing program in 8051.

Right answer is (a) 1

For explanation: The 1D CONTROLLER only have a single ADDRESS register whereas 2D controller have TWO address register and 3D controller have three or more address register.

The correct ANSWER is (a) TIMER and polling

Best explanation: The timeout value can be changed by the PERIPHERAL DEVICES, so for a sophisticated system a COMBINATION of polling and timer is used to check for the signal n times within a predefined interval. This can avoid the bus lock.

Correct option is (b) SCL

To elaborate: The SCL pin can PROVIDE the reference clock for the TRANSMISSION of DATA but it is not a free running clock.

Correct answer is (d) 2D model

The best I can explain: In the 2D model of the DMA controller, an address STRIDE is SPECIFIED which can be used for CALCULATING the offset to the base address at the terminal of count.

Correct choice is (a) master

Easy explanation: The START signal is performed by the master by MAKING the SCL and SDA pin HIGH.

The correct choice is (d) 8250

To explain I would say: The INTEL 8253, 8254 and 8259 are TIMERS WHEREAS Intel 8250 is a UART which is commonly used.

Right choice is (c) SDA and SCL

Easy EXPLANATION: The I2C BUS consists of two LINES which are called SDA and SCL. The master and slave devices are ATTACHED to these lines.

The correct option is (c) 16 MHz

To ELABORATE: The running frequency of the MC68332 is 16 MHz.

Correct option is (b) 1D MODEL

To ELABORATE: The 1D model can implement a circular buffer which makes an AUTOMATIC reset to bring the ADDRESS back to the beginning.

Right answer is (a) DMA controller

The best explanation: The DMA controllers or DIRECT memory access controller provides an efficient METHOD for transferring DATA from the PERIPHERAL to the memory.

Correct choice is (B) null MODEM cable

Easy explanation: The modem CABLES are USED to link PC with other peripherals like printers, plotters, modems etc. But it cannot link with other PCs. So an alternative method is adopted to link PCs which is called null modem cable.

The correct choice is (a) RXRDY

To explain I would say: TheRXRDY and TXRDY are TWO active low pins which are used for ADDITIONAL DMA CONTROL. It can be used for DMA transfers to and from the read and WRITE buffers.

Correct CHOICE is (a) address value

To explain I WOULD say: The address value helps the master to select the device and indicates what operation should be TAKEN. If the 8th BIT is LOGIC one, read operation takes out and if it is logic zero, write operation takes out.

Correct ANSWER is (a) PHILIPS

To ELABORATE: The SPECIAL buffer chip, P82B715 for INCREASING the current drive is developed by Philips.

Correct answer is (a) divide by N

Explanation: The rate GENERATOR mode is DETERMINED by the mode 3 with the Intel 8253. It is a simple divide by N mode where N is the initial VALUE LOADED into the counter.

The CORRECT option is (C) interrupt on TERMINAL count

Explanation: The interrupt on the terminal count is known as mode 0 for the 8253.An initial value is loaded into the count register and then STARTS to count down at the frequency which is determined by the clock input. When the count REACHES zero, an interrupt is generated.