296 + Interview Questions in Digital Electronics in Electronics and Communication Engineering Page 4 InterviewSolution

151.	Which of these are universal gates?
Answer» Both NAND and NOR are called universal gates.

Discussion

152.	Out of latch and flip flop, which has clock input?
Answer» This the main difference between latch and flip-flop. Only flip-flop has clock input.

Discussion

153.	A 4 : 1 multiplexer requires __________ data select line.
Answer» 22 = 4. Hence 2 select lines.

Discussion

154.	The number of unused states in a 4 bit Johnson counter is
Answer» Total state = 2n = 24 = 16 Used state = 2n = 2 x 4 = 8 Unused state = 16 - 8 = 8.

Discussion

155.	Logic analyser is
Answer» It is a multichannel oscilloscope.

Discussion

156.	The minimized version of logic circuit in the given figure is
Answer» The Boolean equation is The circuit in the given figure gives .

Discussion

157.	In the given figure shows a negative logic AND gate. If positive logic is used this gate is equivalent to
Answer» Y = A B = A + B .

Discussion

158.	The function Y = A + AB + A C + BC is to be realized using discrete gates. The inputs available are A, B, C. We need a total of
Answer» Three NOT gates, four AND gates and one OR gate, i.e., total of 8 gates.

Discussion

159.	A 10 bit D/A converter gives a maximum output of 10.23 V. The resolution is
Answer» Resolution = V or 10 mV.

Discussion

160.	As applied to a flip flop the word edge triggered's means
Answer» Edge triggering means the instant when clock transition occurs.

Discussion

161.	A NOR gate is a combination of
Answer» OR and NOT = NOR.

Discussion

162.	The 2's complement representation of - 17 is
Answer» (17)10 = (10001)2 = (-17)10 = 1's complement of (17)2 + 1 the MSB is 0, hence (-17)2 cannot represented in 2's complement representation with 5 bit, therefore (-17) in 2's complement is simply (10001)2 = (17)10 .

Discussion

163.	TTL inverter has
Answer» Data input and control input.

Discussion

164.	4 bit ripple counter and 4 bit synchronous counter are made using flip-flop having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
Answer» In synchronous counter time delay is constant while in Ripple it is additive.

Discussion

165.	The minimum number of NAND gates required to implement the Boolean function A +A + AC is equal to
Answer» A + AB +A B C = A + AB ( 1 + C) = A + AB = A(1 + B) = A.

Discussion

166.	For the K map of the given figure, the simplified Boolean expression is
Answer»

Discussion

167.	9's complement of 12 is
Answer» 99 - 12 = 87.

Discussion

168.	A multiple emitter transistor has many emitters and collectors.
Answer» It has many emitters but one collector.

Discussion

169.	A mode-10 counter can divide the clock frequency by a factor of
Answer» Decade counter is divide by 10 counter.

Discussion

170.	A 4 bit synchronous counter has flip flops having propagation delay of 50 ns each and AND gates having propagation delay of 20 ns each. The maximum frequency of clock pulses can be
Answer» Maximum delay = 50 + 20 = 70 x 10-9 s. Hence .

Discussion

171.	A counter has 4 flip flops. It divides the input frequency by
Answer» 24 = 16.

Discussion

172.	What will be maximum input that can be converted for a 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000).
Answer» .

Discussion

173.	In the given figure shows a logic circuit. The minimum Boolean expression for this circuit is
Answer» Output A(B + C) + AB + C(A + B) = AB + AC + AB + AC + BC = B + A + BC = A + B + C.

Discussion

174.	If number of information bits is 11, the number of parity bits in Hamming code is
Answer» 2p > m + p + 1. If m = 11, p must be 4 to satisfy this equation.

Discussion

175.	The number of digit 1 present in the binary representation of 3 x 512 + 7 x 64 + 5 x 8 + 3 is
Answer» 3 x 512 + 7 x 64 + 5 x 8 + 3 = (2 + 1) x 29 + (4 + 2 + 1)26 + (4 + 1)23 + (2 + 1) = 210 + 29 + 28 + 27 + 26 + 25 + 23 + 21 + 1 = 210 + 29 + 28 + 27 + 26 + 25 + 23 + 21 + 20 9 term of power two Hence number of '1' is 9.

Discussion

176.	A pulse train with a 1 MHz frequency is counted using a 1024 modulus ripple counter using JK flip flops. The maximum propagation delay for each flip-flop should be
Answer» Total delay = = 1 ms = 10 x delay of one flip flop. Therefore delay for one flip-flop = 0.1 ms.

Discussion

177.	The minterm designation for ABCD is
Answer» ABCD = 1111 = m15 .

Discussion

178.	The logic circuit of the given figure is equivalent to
Answer» In the given figure .

Discussion

179.	Out of 5 M x 8, 1 M x 16, 2 M x 16 and 3M x 8 memories, which memory can store more bits?
Answer» Bits are 40 M, 16 M and 32 M.

Discussion

180.	The Boolean expression A ⊕ B is equivalent to
Answer» A ⊕ B = AB + AB

Discussion

181.	Which of these are two state devices?
Answer» Each has 2 states.

Discussion

182.	What will be minimum conversion rate in 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000).
Answer» Minimum conversion rate .

Discussion

183.	A 6 bit ladder A/D converter has input 101001. The output is (assume 0 = 0 V and 1 = 10 V)
Answer» Output = 10 j 6.41 V.

Discussion

184.	A ripple counter has 4 bits and uses flip flops with propagation delay time of 25 ns. The maximum possible time for change of state will be
Answer» In ripple counter all the delays are added.

Discussion

185.	A counter has a modulus of 10. The number of flip flops is
Answer» 23 = 8 and 24 = 16 Therefore 4 flip-flops are needed. Some states will be skipped to give a modulus of 10.

Discussion

186.	The counter shown in the given figure is built using 4 -ve edge triggered toggle FFs. The FF can be set asynchronously when R = 0. The combinational logic required to realize a modulo-13 counter is
Answer» Counter is modulo-13, it will count up to 15 but due to mod-13, it will be reset at 13, (13)10 = (1101 )2 = Q4 Q3 Q2 Q1.

Discussion

187.	Which display device resembles vacuum tube?
Answer» It is similar to triode.

Discussion

188.	The number of inputs and outputs of a full adder are
Answer» Inputs are carry from lower bits and two other bits. Outputs are SUM and CARRY.

Discussion

189.	The dual of A + [B + (AC)] + D is
Answer» In taking dual OR is replaced by AND and vice versa.

Discussion

190.	A divide by 78 counter can be obtained by
Answer» Modulus 13 x modulus 6 = modulus 78.

Discussion

191.	The initial state of MOD-16 down counter is 0110. What state will it be after 37 clock pulses?
Answer» A mod-16 counter goes through 16 states in one cycle of 16 Pulses. It complete 2 cycles in 32 Pulses. In the rest 5 Pulses, it moves down from 0110 = 610 - 510 = 110 or (001)2 .

Discussion

192.	The number of address lines in EPROM 4096 x 8 is
Answer» 212 = 4096.

Discussion

193.	If the inputs to a 3 bit binary adder are 111 and 111, the output will be 110
Answer» 111 + 111 = 1110.

Discussion

194.	A VF display operates on the principle of a vacuum diode.
Answer» It operates on the principle of vacuum triode.

Discussion

195.	In a 3 input NAND gate, the number of states in which output is 0 equals
Answer» Only one input, i.e., A = 1, B = 1 and C = 1 gives low output.

Discussion

196.	ECL is a saturating logic.
Answer» It is a non-saturating logic. Hence highest speed of operation.

Discussion

197.	For the NMOS gate in the given figure, F =
Answer» B + C are in parallel and A is in series with this parallel combination, Similarly D + E are in series. Then D, E are in parallel with A, B and C Y = A(B + C) + DE .

Discussion

198.	The resolution of 4 bit counting ADC is 0.5 volt, for an Analog input of 6.6 volts. The digital output of ADC will be
Answer» Digital output of ADC resolution = .

Discussion

199.	The Boolean expression for the circuit of the given figure
Answer» B and C in parallel give B + C. Similarly D and E in parallel give D + E. (B + C) in series with (D + E) give (B + C) (D + E). Since F is in parallel we get F + (B + C) (D + E). Finally A is in series. Therefore we get A[F + (B + C) (D + E)].

Discussion

200.	What will be BCD number when the output is 0.37 V?
Answer» BCD number is (00110111).

Discussion

Explore topic-wise InterviewSolutions in .

Which of these are universal gates?

Out of latch and flip flop, which has clock input?

A 4 : 1 multiplexer requires __________ data select line.

The number of unused states in a 4 bit Johnson counter is

Logic analyser is

The minimized version of logic circuit in the given figure is

In the given figure shows a negative logic AND gate. If positive logic is used this gate is equivalent to

The function Y = A + AB + A C + BC is to be realized using discrete gates. The inputs available are A, B, C. We need a total of

A 10 bit D/A converter gives a maximum output of 10.23 V. The resolution is

As applied to a flip flop the word edge triggered's means

A NOR gate is a combination of

The 2's complement representation of - 17 is

TTL inverter has

4 bit ripple counter and 4 bit synchronous counter are made using flip-flop having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

The minimum number of NAND gates required to implement the Boolean function A +A + AC is equal to

For the K map of the given figure, the simplified Boolean expression is

9's complement of 12 is

A multiple emitter transistor has many emitters and collectors.

A mode-10 counter can divide the clock frequency by a factor of

A 4 bit synchronous counter has flip flops having propagation delay of 50 ns each and AND gates having propagation delay of 20 ns each. The maximum frequency of clock pulses can be

A counter has 4 flip flops. It divides the input frequency by

What will be maximum input that can be converted for a 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000).

In the given figure shows a logic circuit. The minimum Boolean expression for this circuit is

If number of information bits is 11, the number of parity bits in Hamming code is

The number of digit 1 present in the binary representation of 3 x 512 + 7 x 64 + 5 x 8 + 3 is

A pulse train with a 1 MHz frequency is counted using a 1024 modulus ripple counter using JK flip flops. The maximum propagation delay for each flip-flop should be

The minterm designation for ABCD is

The logic circuit of the given figure is equivalent to

Out of 5 M x 8, 1 M x 16, 2 M x 16 and 3M x 8 memories, which memory can store more bits?

The Boolean expression A ⊕ B is equivalent to

Which of these are two state devices?

What will be minimum conversion rate in 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000).

A 6 bit ladder A/D converter has input 101001. The output is (assume 0 = 0 V and 1 = 10 V)

A ripple counter has 4 bits and uses flip flops with propagation delay time of 25 ns. The maximum possible time for change of state will be

A counter has a modulus of 10. The number of flip flops is

The counter shown in the given figure is built using 4 -ve edge triggered toggle FFs. The FF can be set asynchronously when R = 0. The combinational logic required to realize a modulo-13 counter is

Which display device resembles vacuum tube?

The number of inputs and outputs of a full adder are

The dual of A + [B + (AC)] + D is

A divide by 78 counter can be obtained by

The initial state of MOD-16 down counter is 0110. What state will it be after 37 clock pulses?

The number of address lines in EPROM 4096 x 8 is

If the inputs to a 3 bit binary adder are 111 and 111, the output will be 110

A VF display operates on the principle of a vacuum diode.

In a 3 input NAND gate, the number of states in which output is 0 equals

ECL is a saturating logic.

For the NMOS gate in the given figure, F =

The resolution of 4 bit counting ADC is 0.5 volt, for an Analog input of 6.6 volts. The digital output of ADC will be

The Boolean expression for the circuit of the given figure

What will be BCD number when the output is 0.37 V?