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MICR:

Magnetic Ink Character Reader/Recognition.

BCR:

Bar Code Reader/Recognition.

Distributor or Dealer

An operating system or OS is a software program that enables the computer hardware to communicate and operate with the computer software. Examples for operating systems are Linux, MS-DOS, Windows 8, etc.

• The process of representing an algorithmic solution or a flowchart solution Into a set of instructions in a programming language is called coding.
• Pseudocode is structured English, that consists of short, English phrases used to explain specific tasks within a program’s algorithm.

• C++ offers a predefined data type ‘char’ which is one byte in size and which can hold exactly one character such as an ‘a’ or ‘A’.
• To declare a variable of type char is char ch; 

OOP follows bottom-up approach of programming. Abstraction in OOP is “A model of a complex system that includes only the details essential to the perspective of the viewer of the system.” 

LBs should be submitted to the Government of India latest by December 31st each year for the subsequent financial year. State Secretaries in charge of Rural Development should ensure timely submission of LBs for all districts in their States, to avoid delay in fund release. For this, it is important that the States/districts follow timelines as prescribed in the Operational guidelines of MGNREGS.

LBs received online will be examined in the Ministry and issues, if any, will be communicated to the State for clarification/review. The States will respond to the issues raised so that the LB approval process is initiated.

An Empowered Committee, under the chairmanship of Secretary, Ministry of Rural Development, will assess and approve the State-specific LBs in consultation with the State Secretaries in charge of Rural Development. The Empowered Committee will arrive at a decision on the persondays to be sanctioned based on expected employment generation.

The LB estimate under MGNREGA is based on the amount of total cost (viz. cost towards wage, material and administrative costs) to be incurred while generating a personday wage employment. The expenditure per personday generation of wage employment shall have wage and material costs in the proportion of 60:40. For example, if the cost of the project is Rs. 100, the wage expenditure is at least Rs.60 and the material expenditure is at most Rs. 40. Further, a maximum of Rs. 6 can be utilised towards administrative expenses over and above the wage and material expenses.

As per Para 25(a), Schdeule I, mandatory proactive disclosure of basic information to all common people and stakeholders using a ‘Janata Information System’ should consist of following:

(1) Display at each worksite the ‘Janata’ estimate of the work – showing the details of the work, estimated labour days, quantities of materials to be used in local terminology and item-wise cost of the estimate.

(2) Display on prominent walls or public boards in the village: job cards list, number of days of work provided and the wages paid to each job card holder; and entitlements provided under the Act.

(3) Display through boards at the Gram Panchayat Office: shelf of projects approved, year-wise works taken up or completed by Gram Panchayats and Line Departments, employment provided, funds received and expenditure, list of materials with quantities used in each work, rates at which the material was procured.

(4) Display on the website: The Ministry of Rural Development and the State Departments of Rural Development shall ensure that their websites are updated to fully comply with all the seventeen provisions of Section 4 (1) (b) of the Right to Information Act (22 of 2005) and all information about the Act is available in public domain, through free downloadable electronic form.

Online (default mode): In online mode, the machine on which data are being fed is connected to NREGASoft. 

Offline mode: For using the offline version, NREGASoft is to be downloaded on the machine from a point where internet is available. This version (offline version) is complete in itself. It is a standalone system and all reports can be generated and viewed. Data entry is done in the offline version. 

Online feeding of data is the better of the two options and is therefore, the default option. Offline feeding is an exception and will be permitted by the Ministry only if reliable internet connectivity is not made available at the block level.

NREGASoft has certain in-built checks like:

• Only adults (age 18 and above) can register under MGNREGA.
• The system does not allow allocation of employment for more than 100 days in a year to a household. (however this check can be relaxed if a State is so willing)
• Work allocation cannot be done without demand.
• E-MR can be generated after work allocation only.
• Households are eligible for unemployment allowances if employment has not been provided after 15 days of demand.
• MR will be issued for a period within FY only and cannot spill over to next year.
• Two or more MRs of a work can either be for same period or for disjointed period only.
• Payment date cannot be entered if at least equal amount of funds are not available with paying authority
• Fund transferred from one level should first be received by the other level for further fund utilisation or transfer to other levels.
• Work will be treated as approved only after technical and administrative sanction has been accorded and all details are entered in MIS.
• Measurement Book can be filled only for those activities which are included in technical estimate of work and approved by appropriate authority.
• Only that material can be booked for a work in bill/ vouchers which is entered in technical estimate of work.
• No expenditure can be booked against a work after it is shown as completed in MIS.
• Job card number of the owner of the private land or homestead on which work is taken-up, must be entered along with work details.
• Wage paid cannot be more than MGNREGA notified wage rate.
• A worker cannot be provided employment on different works for same period.

It should act as a forum for concurrent social audit. Its report should be placed at the meeting of the Gram Sabha and also in the public domain. It should be provided an Action Taken Report from the Programme Officer.

The main functions of this cell will be to receive complaints and get it verified, conduct regular field visits to detect irregularities, take suo motu action on reports appearing in the media, review the inspection system, transparency arrangements and functioning of the field and district level vigilance system, initiate recoveries of amounts through the Public Accountants Act in the case of officials and Revenue Recovery Act in the case of others, recommend initiation of disciplinary action against the officials found guilty and frame charges if the reply to the initial memo is unsatisfactory, develop a plan of action for the functioning of the vigilance mechanisms in respect of MGNREGS and send an annual report to State Employment Guarantee Council with suggestions on controlling irregularities and malfeasance.

State Government should empower the Vigilance Cell to initiate disciplinary action, frame charges and then transfer to the disciplinary authority concerned and monitor follow-up action in respect of recoveries, disciplinary action; criminal proceedings.

The District Vigilance Cell will carry out the directions of the State Vigilance Cell. Perform inspections and take follow-up actions for recovery, disciplinary action and filing of criminal cases in respect of non-officials and officials whose disciplinary authority is at the district level. Oversee the functioning of Vigilance and Monitoring Committees at the local level.

Modulus of elasticity decrease with increases of temperature. 

 N^-1m ² OR Pa^-1 

Liquid and gas has no definite shape. 

Advantages of memory mapped I/O scheme over I/O mapped I/O scheme: 

1. The IO read write instructions in I/O mapped I/O require the transfer from an IO port to accumulator. The same data is then transferred to other registers from accumulator thus wasting one instruction and time. But with memory mapped scheme device can do transaction with any of the registers. 

2. The address modes of memory mapped scheme is more powerful than IO mapped IO. So more efficient handling of IO devices can be achieved if they are interface memory mapped IO mechanism.

There are two ways by which we can pass data to microprocessor: 

1. Serial data transfer 

2. Parallel data transfer 

Serial data transfer: - Normally data transfer between two processors mode the data is transferred serially one bit at a time. Due to this the in reduced in size. 

Parallel data transfer: - The programmed I/O data transfer scheme, the user program controls the data transfer. 

Parallel data transfer maybe of two type :-

1. Synchronous: - This type of data transfer is used when device which sends data and devices which receives data are synchronised with the same clock. Works when IO devices and the CPU works with the same speed. IN/OUT instructions are used to transfer data from IO devices to memory and vice versa. Generally used in IO mapped IO scheme, can also be used with memory mapped IO scheme with proper memory read/write instruction. Data is transferred as soon as CPU gives instruction to do so. There is no need to check if the device is ready or not. 

2. Asynchronous: - It means at “regular intervals”. This type of data transfer scheme is used when speed of the IO device does not match with that of CPU. There is no predictability of timing characteristics. The microprocessor always pings the other device to check whether it’s ready or not. During initiation the CPU checks whether device is ready to transfer data, before the actual transfer of data the memory keeps sending signal to IO device. This is called handshaking. The CPU sends initialising signal to device during start and after actual data transfer.

Interrupt Data transfer scheme: -

The program initiates the program and then executes the main program. When IO device is ready to transfer data, the interrupt signal becomes high. The CPU completes the task at hand and then it attends to the IO device. It transfers the data to the stack and then executes a subroutine called ISS (interrupt Service Subroutine). ISS execution transfers data from IO device to memory and vice versa.

Direct memory access: - 

For bulk transfer to or from IO device the above mentioned techniques might prove inefficient. So DMA process is ideal for transferring huge amount of data. The IO device requests the microprocessor by sending a signal. After receiving this request signal the CPU disconnects itself from memory and IO devices by tristating address, data and control bus. The CPU sends the acknowledge signal to IO device. After this data transfer takes place, and on completion IO device withdraws DMA request.

• The direct memory access in minimum mode is facilitated by HOLD and HLDA signals. 
• When the external devices wants access the memory directly it request through a high signal at HOLD pin. 
• The 8086 microprocessor samples the HOLD signal at low high transition of clock. 
• The 8086 microprocessor acknowledge the holds request by making the HLDA (HOLD Acknowledgement) high at the end of current bus cycle. 
• The external device accesses the memory and after completion of task it withdraw the HOLD request by making the signal at HOLD pin low. 
• The 8086 microprocessor check the HOLD pin at every low to high transition of clock .After detecting the low signal at HOLD it will make the signal at HLDA low.

Cache memory: - 

To speed up execution of data, a buffer between the CPU and memory is used. It consists of high speed static ram. Execution speed is equal to microprocessor speed.

DMA In maximum mode (MN/MX’=0):- 

• In maximum mode two signal RQ’/GT0’ and RQ1’/GT1’ are used for direct memory access operation. 
• The DMA request and DMA acknowledgment signal are received on same line. 
• Thus RQ’/GT0’ and RQ1’/GT1’ are two channels for DMA by which two separate external devices can access memory directly. 
• The external device make a request for DMA by sending a low pulse at RQ’/GT’ ,The 8086 microprocessor samples the RQ’/GT’ signal at low to high transition of clock period. 
• The 8086 microprocessor acknowledgement the DMA request at the end of current bus cycle by sending a low pulse on the same RQ’/GT’ pin .The address/data and control signal float at the same time. 
• After competition of memory operation the external devices informs the 8086 microprocessor by sending a low pulse on the RQ”/GT’ pin .The 8086 microprocessor by sending a low on this pin and low –to-high transition of clock regains the control of lines.

Pipelining:-

This is used to speed up execution of instruction. While the execution unit is working on instructions, the queue in a CPU fetches the next set of instructions. As soon as the working on instruction is over, the next set of instructions are fed into the execution unit. There is no time wasted in fetching instructions. This technique is called pipelining.

HLT AND WAIT STATE:-

On the execution of HLT (Halt) instruction of 8086 ,CPU suspends its instruction execution and enters into an idle state .It waits for either an external hardware interrupt or treat or a reset pin (interrupt).When any one of these occurs ,CPU starts executing again. When the wait instruction is executed by 8086 .it internally checks the logic level existing at its TEST’ input .If TEST’ is at logic 1 state ,then CPU goes into an idle state .When TEST’ input assume a zero state execution resume from the next sequential instruction in the program.

EXECUTION UNIT: 

1. The execution unit contains the register. 

2. It has 16 bit ALU, able to perform arithmetic and logical operations. 

3. The 16 bit flag register reflects the result of execution by the ALU. 

4. The decoding unit decodes the opcode bytes issued from the instruction byte queue. 

5. The execution unit may pass the result to the bus interface unit for storing them in memory.

BUS INTERFACE UNIT (BIU): 

1. The bus interface unit contains the circuit for physical address calculation and pre decoding instruction byte queue. 

2. The BIU makes the system bus signal available for external interfacing of the device. 

3. The unit is responsible for establishing communication with external device and peripherals are including memory via the bus. 

4. The complete physical address from contents which is 20bits long is generated using segment and offset register. 5. For a generation of physical address from contents of these two registers the content of a segment register also called as segment address is shifted left bit wise 4-times and to this result, content of an offset register also called an offset address is added to produce a 20 bit physical address. 

6. The bus interface unit has a separate address to perform this procedure for obtaining a physical address while addressing mode the segment address values is to be taken from an appropriate segment register depending upon the offset may be the content of IP, BX,SI,DI,SP,BP or an intermediate 16 bit values depending upon addressing mode.

7. In case of 8085 once operational code is fetched and decoded the external bus remain free for same time while the processor internally executes. While the fetched instruction is executed internally, the external bus is used to fetch the machine code of the next instruction and arrange it I a queue known as “PREDECODED INSTRUCTION BYTE QUEUE”. 

8. The operational code is fetching by BIU and EU executes the previously decode instruction concurrently. The BIU along with the EU perform a pipe line. 

9. The BIU thus manages the complete interface execution unit with memory and input and output decides under the control of timing and control unit.

Multitasking or memory management: - 

Due to growth in hardware complexity of computers, they were used in time sharing working environment. That means a fixed amount of time is allocated to different programmes. To achieve relocatablity segmented scheme is used.

The uniform for a hockey player includes a shirt, a nicker, socks, shoes. A goal-keeper needs pads and gloves also.

Correct answer is: (C) [Ctrl]+[Shift]

Virtual memory system:-

In this scheme the complete program is divided into several pgs. and stored in hard disk. At same time the main memory is divided into small pages.

By this we can swap the pages between hard disk and main memory. This task is performed by the operating system. Main memory size is bigger than physical memory size which is correct.

The evolution of microprocessor was divided into four generations :

FIRST GENERATION : 

The first microprocessor is intel 4004. PMOS microprocessor introduced in he year 1971 nt the intel corporation, USA. The enhanced version of this is intel 4040. Memory addressing capacity is 1kb, clock frequency is 750 khz. No of pins is 16 and clock freq is defined as the no instruction that can be executed in one sec.

eg. Rockwell international’s PPS-4, TOSHIBA t3472 etc.

SECOND GENERATION 

The first 8 bit is microprocessor is intel 8008 introduced in the year 1972 which is a 8 bit pmosmicroprocessor .in the year 1973, intel 8080 which is an 8 bit, nmos microprocessor was in traduced which is faster and compatible to TTL than that of pmos technology. But intel 8080 requires three power supplies so in the year 1975 intel 8085 , an 8 bit nmos microprocessor was introduced which requires one power supply ie +5v dc. Memory addressing : -64 kb , clock frequency – 1mhz to 6mhz. No of pins 40. 

eg. Rockwell international’s PPS 8, ZILOG’s z-800 etc.

THIRD GENERATION

In 1975, a 16 bit microprocessor was developed which is anhmos microprocessor. Memory addressing capacity: i mb to 16 mb, clock frequency 6 to 12.5 mhz, no of pins -40 

eg. Intel 8088, 80186, 80286

Intel 80186 and 80188 are integrated microprocessors beside cpu. They contain some additional components that are PIC, DMA, PC Or timer, clock generator, peripheral chip select logic. Programmable state generator and local bus controller etc. In intel 80286 besides cpu it has integrated memory management unit, four level memory protections, it supports virtual memory and operating systems.

FOURTH GENERATION 

After 1980, 32 bit microprocessors were produced. The first 32 bit microprocessor is iAPX 432. This is not popular as it is eventually disconnected. The most powerful and very popular 32 bit microprocessor is intel 80386. In short it is called intel-386. Memory addressing capacity 4gb, clock frequency-20 mhz to in ghz. No of pins is 132 or more. 

eg. Pentium pro, Pentium II xenon, Pentium II celerum , Pentium III.

Correct answer is: (D) =AND (C4<10, D4,100)

The weight of a hockey stick for men is 28 ounce and 23 ounce for women.

Correct answer is: (C) Name Box

LIMITATION OF 8 BIT MICROPROCESSORS: 

1. LOW SPEED OF EXICUTION 

2. LOW MEMORY ADDRESSING CAPABILITY 

3. LIMITED NUMBER OF GENERAL PURPOSE REGISTERS 

4. LESS POWERFUL INSTRUCTION SET.

PIN CONFIGURATION OF 8086: 

1. Pin configuration of 8086 microprocessors available in three clock rates, 5 MHZ,8 MHZ,10 MHZ. 

2. It is fabricated by HMOS technology and package in a 40 pin DIP (dual in package). 

3. It can be operated in single processors or multiple processors configuration etc.

COMMON PINS IN 8086: 

ADDRESS AND DATA BUS (AD₀-AD₁₅): 

• Pin 2-16, 39(TYPES- INPUT /OUTPUT OPERATIONS). 

FUNCTIONS: These are the time multiplexed memory input , output address and data bus pins. The address part (A₀-A₁₅) is transferred in T₁ clock cycle and data are transferred in T₂, T₃, T_W, T₄ clock cycle. These signals are stored by address latch enable (ALE) signals generated at a beginning of T₁ states these AD₀- AD₁₅ pins are traced in order to make AD₀-AD₁₅ lines receive the data signal.

Goal board is 4 yards long and not higher than 18 inches.

The length of a football ground should not be more than 130 yards and less than 100 yards. Its breadth should not be more than 100 yards and less than 50 yards.

FEATURES OF 8086: 

1. The 8086 is a 16-bit N-channel, H-MOS Microprocessor. 

2. It’s CMOS version is available in “80C86” 

3. It consumes less power. 

4. It is introduced in 1978 

5. It contains an electronic circuit of 29000 transistors 

6. It is built on a single semiconductor chip and packaged in 40-pin IC packing. 

7. It has 20 address lines and 16 data lines 

8. It can directly address up to 220, , which is nearly equal to 1M bytes of memory 

9. It has 16 bit registers for symmetrical operations 

10. It has 24 operand addressing mode 

11. It can support 8 &16 bit signed and unsigned arithmetic in binary or decimal 

12. Multi bus compatible system interface. etc.

Pin number 35-38 

• Type – output 

• Function:- 

These pins are called address/ status pin in T1 state a high on these pins specifies a memory operation and low specific input / output operations the status information is available on that line during T2, T3 and T4 clock cycles. The S5 pin is used to show the status interrupt flag at the beginning of each clock cycle A16/S3 and A17/S4 are encoded as shown in table.

A goal post is 4 yards in length and 7 feet in height

All the lines of a football ground are 5 centimetre wide.

Penalty kick takes place from a distance of 16 yards.

The INTEL 8086 contains the following register 

(a) General purpose register 

(b) Pointer and index register 

(c) Segment register 

(d) Instruction pointer 

(e) Status Flags

When the ball crosses the line in between the goal posts the goal takes place.