Explore topic-wise InterviewSolutions in .

C) It takes me an hour.

(i) C. Carbon dioxide

(ii) B. Carbon dioxide

(iii) B. Blue - black colour would be obtained on the leaf of plant B

(iv) C. i. and iii

C) I visited museums, theatres, libraries.

(i) C. Carbon dioxide

(ii) B. Carbon dioxide

(iii) B. Blue - black colour would be obtained on the leaf of plant Y and no change in colour on leaf of plant X.

(iv) C. i. and iii

(I) C. CaCO₃

(II) C. 18 g

(III) A. Brine

(IV) A. Between 1 to 3

Correct option is B. X, Y, Z

C) So did my son.

Correct option is B. 1.21

Refractive index of flint glass w.r.t alcohol = \(\frac{R.I \,of \,flint \,glass}{R.I \,of \,alcohol}\) 

= \(\frac{1.65}{1.36}\) = 1.21

Correct answer –(B)1.21

Correct option is D. Urine is more diluted.

Correct option is D. -80/3 cm 

m = -3 

V = 80cm 

m = v/u 

-3 = 80/u 

u = 80/−3 = −80/3 cm. 

Correct answer = (D) −80/3 cm.

Correct option is D. Medium 1 and 3 are essentially the same medium, but medium 2 is denser than 1 and 3

Correct option is C. ii, iii and iv

Equity Shares 

Features of Equity shares: 

(a) Equity share capital serves as permanent capital as it is to be repaid only at the time of liquidation. 

(b) Payment of dividend is not compulsory. 

(c) Funds can be raised through equity shares without creating charge on the assets of the company.

 Correct answer is d. Consistency

 Correct answer is c. Public relations coordinators

 Correct answer is c. Concierge

3sin 10° – 4sin 10° = sin3.10° 

= sin30° = \(\frac{1}{2}\)

Correct Answer is \(\frac{-\pi}{3}\)

Now, let x = \(cosec^-1\left(cosec\frac{4\pi}{3}\right)\)

⇒ cosec x =cosec ( \(\frac{4\pi}{3}\)) 

Here range of principle value of cosec is [\(-\frac{\pi}{2},\frac{\pi}{2}\) ] 

⇒ x =\(\frac{4\pi}{3}\)∉ [\(-\frac{\pi}{2},\frac{\pi}{2}\) ] 

Hence for all values of x in range [\(-\frac{\pi}{2},\frac{\pi}{2}\) ] ,the value of 

\(cosec^-1\left(cosec\frac{4\pi}{3}\right)\) is 

⇒ cosec x =cosec (π+ \(\frac{\pi}{3}\)) (\(\because\) cosec ( \(\frac{4\pi}{3}\))= cosec ( π+ \(\frac{\pi}{3}\)) ) 

⇒ cosec x =cosec (-\(\frac{\pi}{3}\)) (\(\because\) cosec (π + θ)= cosec(-θ)) 

⇒ x = -\(\frac{\pi}{3}\)

An equivalent representation for the Boolean expression A’ + 1 is 1

Two, four and eight variables are reduced by a pair, quad and octet respectively.

Special functions of general-purpose registers:

AX & DX registers:

In 8 bit multiplication, one of the operands must be in AL. The other operand can be a byte in memory location or in another 8 bit register. The resulting 16 bit product is stored in AX, with AH storing the MS byte. 

In 16 bit multiplication, one of the operands must be in AX. The other operand can be a word in memory location or in another 16 bit register. The resulting 32 bit product is stored in DX and AX, with DX storing the MS word and AX storing the LS word. 

BX register :

In instructions where we need to specify in a general purpose register the 16 bit effective address of a memory location, the register BX is used (register indirect). 

CX register :

In Loop Instructions, CX register will be always used as the implied counter.

In I/O instructions, the 8086 receives into or sends out data from AX or AL depending as a word or byte operation. In these instructions the port address, if greater than FFH has to be given as the contents of DX register.

Ex :IN AL, DX 

DX register will have 16 bit address of the I/P device 

Physical Address (PA) generation :

Generally Physical Address (20 Bit) = Segment Base Address (SBA) + Effective Address (EA) 

Code Segment :

Physical Address (PA) = CS Base Address + Instruction Pointer (IP)

Data Segment (DS)

PA = DS Base Address + EA can be in BX or SI or DI Stack Segment (SS) 

PA + SS Base Address + EA can be SP or BP 

Extra Segment (ES)

PA = ES Base Address + EA in DI 

Instruction Format :

The 8086 instruction sizes vary from one to six bytes. The OP code occupies six bytes and it defines the operation to be carried out by the instruction. 

Register Direct bit (D) occupies one bit. It defines whether the register operand in byte 2 is the source or destination operand. 

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Byte 3 Byte 4 

D=1 Specifies that the register operand is the destination operand. 

D=0 indicates that the register is a source operand. 

Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data 

W=0 indicates 8 bit operation 

W=1 indicates 16 bit operation 

7 2 1 0 7 6 5 4 3 2 1 0 

Opcode D W MOD REG R/M 

Low Disp/ 

DATA 

High Disp/ 

DATA

The second byte of the instruction usually identifies whether one of the operands is in memory or whether both are registers. 

This byte contains 3 fields. These are the mode (MOD) field, the register (REG) field and the Register/Memory (R/M) field.

F = A'B'+ C'+ D'+ E'

Taking complement on both sides:

F’ = (A'B'+ C'+ D'+ E')’ =(A’B’)’.(C’)’(D’)’(E’)’ 

=(A+B).C.D.E

So, (A + B)CDE represents correct expression for F’

MOD (2 bits) Interpretation :

00 Memory mode with no displacement follows except for 16 bit 

displacement when R/M=110 

01 Memory mode with 8 bit displacement 

10 Memory mode with 16 bit displacement 

11 Register mode (no displacement) 

Register field occupies 3 bits. It defines the register for the first operand which is specified as source or destination by the D bit. 

Byte 1 Byte 2 OR 

Register Operand/Register to use EA 

Calculation 

Register Operand/Extension of opcode 

Register mode/Memory mode with 

displacement length 

Word/byte operation 

Direction is to register/from register 

Operation code 

DIRECT ADDRESS LOW BYTE 

DIRECT ADDRESS HIGH BYTE 

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REG W=0 W=1 

000 AL AX 

001 CL CX 

010 DL DX 

011 BL BX 

100 AH SP 

101 CH BP 

110 DH SI 

111 BH DI

The R/M field occupies 3 bits. The R/M field along with the MOD field defines the second operand as shown below. 

MOD 11 

R/M W=0 W=1 

000 AL AX 

001 CL CX 

010 DL DX 

011 BL BX 

100 AH SP 

101 CH BP 

110 DH SI 

111 BH DI 

Effective Address Calculation 

R/M MOD=00 MOD 01 MOD 10 

000 (BX) + (SI) (BX)+(SI)+D8 (BX)+(SI)+D16 

001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16 

010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16

 011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D10 

100 (SI) (SI) + D8 (SI) + D16

101 (DI) (DI) + D8 (DI) + D16 

110 Direct address (BP) + D8 (BP) + D16 

111 (BX) (BX) + D8 (BX) + D16 

In the above, encoding of the R/M field depends on how the mode field is set. If 

MOD=11 (register to register mode), this R/M identifies the second register operand. 

MOD selects memory mode, then R/M indicates how the effective address of the memory operand is to be calculated. Bytes 3 through 6 of an instruction are optional fields that normally contain the displacement value of a memory operand and / or the actual value of an immediate constant operand. 

Example 1 : MOV CH, BL 

This instruction transfers 8 bit content of BL

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Into CH 

The 6 bit Opcode for this instruction is 1000102 D bit indicates whether the register specified by the REG field of byte 2 is a source or destination operand. 

D=0 indicates BL is a source operand. 

W=0 byte operation 

In byte 2, since the second operand is a register MOD field is 11 The R/M field = 101 (CH)

Register (REG) field = 011 (BL) 

Hence the machine code for MOV CH, BL is 

10001000 11 011 101 

Byte 1 Byte2 

= 88DD16 

Example 2 : SUB Bx, (DI) 

This instruction subtracts the 16 bit content of memory location addressed by DI and DS from Bx. The 6 bit Opcode for SUB is 001010

D=1 so that REG field of byte 2 is the destination operand. W=1 indicates 16 bit operation. 

MOD = 00 

REG = 011 

R/M = 101 

The machine code is 0010 1011 0001 1101 

2 B 1 D

2B1D16 

Summary of all Addressing Modes 

Example 3 : Code for MOV 1234 (BP), DX 

Here we have specify DX using REG field, the D bit must be 0, indicating the DX is the source register. The REG field must be 010 to indicate DX register. The W bit must be 1 to indicate it is a word operation. 1234 [BP] is specified using MOD value of 10 and R/M value of 110 and a displacement of 1234H. The 4 byte code for this instruction would be 89 96 34 12H. 

MOD / R/M Memory Mode (EA Calculation) Register Mode 00 01 10 W=0 W=1 

000 (BX)+(SI) (BX)+(SI)+d8 (BX)+(SI)+d16 AL AX 

001 (BX) + (DI) (BX)+(DI)+d8 (BX)+(DI)+d16 CL CX 

010 (BP)+(SI) (BP)+(SI)+d8 (BP)+(SI)+d16 DL DX 

011 (BP)+(DI) (BP)+(DI)+d8 (BP)+(DI)+d16 BL BX 

100 (SI) (SI) + d8 (SI) + d16 AH SP 

101 (DI) (DI) + d8 (DI) + d16 CH BP 

110 d16 (BP) + d8 (BP) + d16 DH SI

111 (BX) (BX) + d8 (BX) + d16 BH DI 

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Opcode D W MOD REG R/M LB displacement HB displacement 

100010 0 1 10 010 110 34H 12H 

Example 4 :Code for MOV DS : 2345 [BP], DX 

Here we have to specify DX using REG field. The D bit must be o, indicating that Dx is the source register. The REG field must be 010 to indicate DX register. The w bit must be 1 to indicate it is a word operation. 2345 [BP] is specified with MOD=10 and R/M = 110 and displacement = 2345 H. 

Whenever BP is used to generate the Effective Address (EA), the default segment would be SS. In this example, we want the segment register to be DS, we have to provide the segment override prefix byte (SOP byte) to start with. The SOP byte is 001 SR 110, where SR value is provided as per table shown below.

(A + B)'(C + D + E)' + (A + B)'=(A+B)’((C+D+E)+1) (Distb. Law)

=(A+B)’.1 (Identity Law)

=(A+B)’ (Identity Law)

=A’B’ (DeMorgan’s Law)

So, simplification of the Boolean expression (A + B)’(C + D + E)’ + (A + B)’ yields 

Principle of Duality is a very important principle used in Boolean algebra. This states that starting with a Boolean relation, another Boolean relation can be derived by :

1.  Changing each OR sign (+) to an AND sign(.).

2.  Changing each AND sign (.) to an OR sign(+).

3.  Replacing each 0 by 1 and each 1 by 0

XZ + Z(X'+ XY)= XZ + X’Z + XYZ   (distributive Law)

= Z(X+X’) + XYZ    (distributive Law)

= Z(1) + XYZ       (Complementarity Law)

= Z+XYZ (Identity Law)

The equivalent most simplified Boolean representation for F is Z+XYZ

(a) Correct

(b) Correct

(c) Correct

(d) Incorrect. Correct form is A . A’ = 0

(e) Correct

(f) Correct

(g) Incorrect. Correct form is (A + B)’ = A’B’

(h) Incorrect. Correct form is (AB), = A’ + B

(i) Correct

(j) Correct

(k) Correct

(l) Incorrect. Correct form is X + YZ = (X + Y)(X + Z)

(A+B+C)(D+E)' + (A+B+C)(D+E)

= (A+B+C)((D+E)+(D+E)’) (Distributive Law)

= (A+B+C).(1) (X+X’=1)

= A+B+C

So, simplification of the Boolean expression (A + B + C)(D + E)’ + (A + B + C)(D + E) yields A+B+C 

SR Segment register 

00 ES 

01 CS 

10 SS 

11 DS 

To specify DS register, the SOP byte would be 001 11 110 = 3E H. Thus the 5 byte code for this instruction would be 3E 89 96 45 23 H. 

SOP Opcode D W MOD REG R/M LB disp. HD disp. 

3EH 1000 10 0 1 10 010 110 45 23 

Suppose we want to code MOV SS : 2345 (BP), DX. This generates only a 4 byte code, without SOP byte, as SS is already the default segment register in this case. 

Example 5 : 

Give the instruction template and generate code for the instruction ADD OFABE [BX], [DI], DX (code for ADD instruction is 000000) 

ADD OFABE [BX] [DI], DX 

Here we have to specify DX using REG field. The bit D is 0, indicating that DX is the source register. The REG field must be 010 to indicate DX register. The w must be 1 to indicate it is a word operation. FABE (BX + DI) is specified using MOD value of 10 and R/M value of 001 (from the summary table). The 4 byte code for this instruction would be 

Opcode D W MOD REG R/M 16 bit disp. =01 91 BE FAH 000000 0 1 10 010 001 BEH FAH 

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Example 6 :

Give the instruction template and generate the code for the instruction MOV AX, [BX]

(Code for MOV instruction is 100010) 

AX destination register with D=1 and code for AX is 000 [BX] is specified using 00 Mode and R/M value 111

It is a word operation 

Opcode D W Mod REG R/M =8B 07H 

100010 1 1 00 000 111

The relationship x * x’ + y = xy represents the dual of the Boolean property x + x’y = x + y

The relationship that represents the dual of the Boolean property A + 1 = 1 is A . 0 = 0 

Data Transfer Instructions : 

The MOV instruction is used to transfer a byte or a word of data from a source operand to a destination operand. These operands can be internal registers of the 8086 and storage locations in memory.

Mnemonic Meaning Format Operation Flags affected 

MOV Move MOV D, S (S) → (D) N o n e 

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Destination Source Example

Memory Accumulator MOV TEMP, AL 

Accumulator Memory MOV AX, TEMP 

Register Register MOV AX, BX 

Register Memory MOV BP, Stack top

Memory Register MOV COUNT [DI], CX

Register Immediate MOV CL, 04 

Memory Immediate MOV MASK [BX] [SI], 2F 

Seg. Register Reg 16 MOV ES, CX 

Seg. Register Mem 16 MOV DS, Seg base 

(Word Operation) Reg 16 SegReg MOV BP SS 

(Word Operation) Memory 16 SegReg MOV [BX], CS 

MOV instruction cannot transfer data directly between a source and a destination that both reside in external memory

(i)  X + X’ = 1

(ii)  X . 1 = X

The dual of 1 + 1 = 1 is 0. 0 =0

INPUT/OUTPUT INSTRUCTIONS : 

IN acc, port :

In transfers a byte or a word from input port to the AL register or the AX register respectively. The port number my be specified either with an immediate byte constant, allowing access to ports numbered 0 through 255 or with a number previously placed in the DX register allowing variable access (by changing the value in DX) to ports numbered from 0 through 65,535. 

In Operands 

Example 

acc, immB IN AL, 0E2H (OR) IN AX, PORT 

acc, DX IN AX, DX (OR) IN AL, DX 

OUT port, acc:

Out transfers a byte or a word from the AL register or the AX register respectively to an output port. The port numbers may be specified either with an immediate byte or with a number previously placed in the register DX allowing variable access.

No flags are affected.

In Operands Example

Imm 8, acc OUT 32, AX (OR) OUT PORT, AL 

DX, acc OUT DX, AL (OR) OUT DX, AX 

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XCHG D, S : 

Mnemonic Meaning Format Operation Flags affected 

XCHG Exchange XCHGD,S (D) ↔ (S) None 

Destination Source Example 

Accumulator Reg 16 XCHG, AX, BX 

Memory Register XCHG TEMP, AX 

Register Register XCHG AL, BL 

In the above table register cannot be a segment register 

Example : For the data given, what is the result of executing the instruction. 

XCHG [SUM], BX 

((DS) + SUM) ↔ (BX) 

if (DS) = 0200, SUM = 1234 

PA = 02000 + 1234 = 03234 

ASSUME (03234) = FF [BX] = 11AA 

(03235) = 00 

(03234) ↔ (BL) 

(03235) ↔ (BH) 

We get (BX) = 00FF 

(SUM) = 11AA

XLAT (translate)

This instruction is useful for translating characters from one code such as ASCII to another such as EBCDIC, this is no operand instruction and is called an instruction with implied addressing mode. 

The instruction loads AL with the contents of a 20 bit physical address computed from DS, BX and AL. This instruction can be used to read the elements in a table where BX can be loaded with a 16 bit value to point to the starting address (offset from DS) and AL can be loaded with the element number (0 being the first element number) no flags are affected. 

XLAT instruction is equivalent to 

MOV AL, [AL] [BX] 

AL ← [(AL) + (BX) + (DS)] 

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(b)  x + y + z’ 

(e)  x’y’ + y’z

Let the binary number is stored at 0350 and its equivalent gray code is stored at 0351 after the program execution. 

Look up table is as follows. 

Memory Data Data in look up table 0300 00 

Exampe: If (0350) = 03 Result (0351) = 02 0301: 01 0302 03 0303 02

030F 08 

MOV BX, 0300 : Let BX points to the starting address of the look up table. 

MOV SI, 0350 : Let SI points to the address of binary numbers 

LOD SB : Load the string byte into AL register. 

XLAT : Translate a byte in AL from the look up table stored in the memory pointed by BX. MOV [SJ+1], 

AL : Move the equivalent gray code to location SI+1 INT20

(c) NAND  gate

Truth Table is a table which represents all the possible values of logical variables/statements along with all the possible results of the given combinations of values

Inverted AND gate is called NAND gate and Inverted OR gate is called NOR gate. 

Heat rate is defined as the heat supplied in to the plant in Btu by power generated or output by the plant in kWh. 

Heat rate = Heat supplied in Btu / Power output in kWh. 

Gray code does not follow binary progression, instead in gray code each successive number differs only in one place. 

The other name of NOT gate is Inverter gate.

TG rotor is made up of alloy steel and blades are made up of stainless steel.