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The correct ANSWER is (d) unified

The explanation is: The INTEL 80486DX processor has a unified cache. Similarly, Motorola MPC601PC also uses the unified cache. The unified cache has the same mechanism to STORE both DATA and instructions.

Correct choice is (b) MC68030

The explanation: MC68030 uses a LINEAR burst FILL WHEREAS MC68040, US 74707 B2 uses to wrap AROUND burst INTERFACING. HyperBus can switch to both linear and wrap around interfacing.

Correct choice is (d) memory protection UNIT

For explanation I would say: The memory MANAGEMENT unit and the memory protection unit PROVIDES security to the PROCESSOR by trapping the invalid memory accesses before they corrupt other data.

The correct option is (a) direct memory access

The explanation is: The DMA is direct memory access which can modify the memory WITHOUT the help of the processor. If any kind of memory access by DMA to be done, it will PASSES a REQUEST to the processor BUS and the processor provides an acknowledgment and gives the control of the bus to the DMA.

Correct choice is (b) ARM protection memory management unit

For explanation I would say: In the ARM protection architecture, the memory is divided into some regions of size 4 KBYTES to 4 Gbytes. These regions possess bits called the cacheable bit, buffer bit, and access permitted bits. The regions are numbered as per priority level for which the PERMISSION bits TAKES the precedence if any of the regions gets overlapped.

Right option is (b) paged memory management unit

The best I can explain: The paged memory management unit is used to decrease the amount of STORAGE needed in the page TABLES, that is, a multi-level tree STRUCTURE is used. MC68030, PowerPC, ARM 920 USES a paged memory management unit.

The CORRECT answer is (B) physical address

To elaborate: The LOGICAL address is the address generated by the CPU. It is also KNOWN as VIRTUAL address. The physical address is the address which is seen by the memory unit.

The correct ANSWER is (b) 2

Easiest explanation: In the burst interface, the first access of the memory address requires two clock CYCLES and a single cycle for the REMAINING memory address.

Correct ANSWER is (a) permission bit

For explanation: The ARM ARCHITECTURE memory protection unit divides the memory range into different regions of size ranging from 4 Kbytes to 4 Gbytes. Each region is associated with certain BITS called the cacheable bit, buffer bit, and access permitted bit. These bits are SIMILAR to the permission bit in the ARM memory management unit architecture which is stored in the control register.

Right answer is (B) 2

Easy explanation: There are two types of descriptor table used by the PROCESSOR in the protected MODE which are GDT and LDT, that is global descriptor table and LOCAL descriptor table RESPECTIVELY.

Right CHOICE is (a) write-allocate cache

To explain: A write-allocate cache allocates the ENTRIES in the cache for any data that is written out. If the data is transferred to the EXTERNAL memory so that, when it is accessed again, the data is already waiting in the cache. It works efficiently if the size of the cache is large and it does not overwrite even though it is ADVANTAGEOUS.

Right OPTION is (a) error signal

Best EXPLANATION: If memory ACCESS from the software does not access the correct data, an error signal is generated which will start a SUPERVISOR level software for the decision.

The CORRECT OPTION is (a) MESI protocol

To explain I would say: MPC601 uses a MESI protocol, that is they have a shared state for data accessing in the cache. It can reduce the cache coherency but the cache coherency is processor specific. So different processors have different cache coherency implementations.

Correct OPTION is (a) index MECHANISM

For explanation I would SAY: The index mechanism splits the EXTERNAL memory storage into a series of memory pages in which each page is the same size as the cache. Each page is MAPPED to the cache so that each page can have its own location in the cache.

Correct choice is (c) timing ISSUES

For explanation: When the REFRESH cycle in a DRAM is running, it will not access data, so the PROCESSOR will have to WAIT for its data. This ARISES some timing issues.

The CORRECT option is (a) 1 M

To explain I would say: The 8086 PROCESSOR has a 20-bit address bus, HENCE it can access a MEMORY of 2^20-1 M locations.

Right answer is (a) endianness

The explanation: Endianness DEFINES the order of BYTES, that is, whether it is big endian or little endian. The former represents the higher order BITS and the LATTER represents the lower order bits.

Correct choice is (a) INTEL

Easy explanation: Miniature Card is an SRAM MEMORY card proposed by Intel in the 1980s but it was no longer MANUFACTURED.

Right choice is (a) SRAM

Easiest explanation: SRAM have more speed than DRAM because it has 4 to 6 transistors arranged as flip-flop logic gates, that is it can be FLIPPED from one BINARY state to another but DRAM has a small capacitor as its storage element.

The correct choice is (C) DIMM

To explain I would say: DIMM is a special version of SIMM which is 168-bits wider BUS and looks similar to a larger SIMM. The wider bus INCREASES the memory speed and change in SUPPLY VOLTAGE.

Correct option is (C) virtual memory technique

Best explanation: In the workstation and in the UNIX operating SYSTEM virtual memory technique is FREQUENTLY USED in which the main memory is divided into different segments and pages. These pages will have a virtual address which can increase the address spacing.

Right choice is (C) TLB

Easiest explanation: The TRANSLATION lookaside buffer is common cache memory seen in almost all CPUs and desktops which are a part of the memory MANAGEMENT UNIT. It can improve the virtual ADDRESS translation speed.

Correct ANSWER is (a) relative addressing mode

Easiest explanation: The memory allocation of the modular blocks can be done by the writing the software PROGRAM in relocatable or POSITION independent manner which can execute ANYWHERE in the memory map, but relocatable code must have the same ADDRESS between its data and code segments. This is used to avoid the use of absolute addressing modes which is replaced by the relative addressing modes.

The correct choice is (c) transistor

The explanation is: FOUR to six transistors are used to store a SINGLE bit of data and FORM a flip-flop logic gate and THUS SRAM is faster in accessing data.

Correct choice is (a) stack

The explanation is: A stack is a MEMORY which is ALLOCATED to the PROGRAM in last-in, first out pattern. Stack pointer contains the memory ADDRESS of the stack.

The correct choice is (a) by asserting CAS before RAS

The EXPLANATION: CBR WORKS by an internal address counter which is PERIODICALLY INCREMENTED. The mechanism is based on CAS before RAS. Each TIME when RAS is asserted, the refresh cycle performs and the counter is incremented.

Correct answer is (a) 100ns

The best I can explain: The access TIME of memory is DEFINED as the maximum time TAKEN by the chip to read/write data and it is very IMPORTANT to MATCH the access time to the design. For example, MCM51000AP10 have 100ns access time for the memory.

Correct choice is (a) delays

For explanation: The delays occurring in the memory MANAGEMENT UNIT can destroy the accuracy in the ALGORITHMS and in order to avoid this, the linear ADDRESSING RANGE should be increased.

The correct CHOICE is (c) Zig-zag

Explanation: Zig-zag package of MEMORY is a PLASTIC package used for DRAM. The LEADS of this package are arranged in a zigzag manner.

Right ANSWER is (c) stacked-cell

Explanation: Stacked-cell can store greater than 1 GB. Planar CAPACITOR can store up to 1 Mb and trench capacitor can store 4-256 Mb.

Correct option is (c) BURST mode

For explanation: The page mode, nibble mode devices can provide data fastly when the new column ADDRESS is given. In burst mode operation, the PROCESSOR can fetch more data than it needs and keeps the remaining data in an internal cache for the future use which can reduce the need for FAST STATIC RAMs.

The CORRECT choice is (C) page mode

To explain: The page mode operation have MEMORY CYCLES that exhibit some form of locality, that is, stay within the page boundary which causes page missing when there is access outside the page boundary and two or more wait STATES.

The correct OPTION is (a) TTL

Best explanation: TTL or TRANSISTOR-transistor LOGIC which is a type of bipolar junction transistor access data very fastly but consumes lots of power WHEREAS CMOS is used in low power consumption.

The correct OPTION is (d) number of data lines and the width of the data PATH from the processor

Explanation: The MINIMUM number of chips is determined by the number of data lines and the width of the data path from the processor. For example, MC6800 family have a 16-bit wide datapath, 16*1 devices, 4*4 or 2*8 devices are needed.

The CORRECT answer is (b) 4-256 Mb

Easy EXPLANATION: TRENCH capacitor can STORE from 4-256 Mb but planar capacitor can store up to 1 Mb.

Correct choice is (a) software

The explanation is: The cache performance is completely dependent on the system and software. In software, the processor checks out each LOOP and if a duplicate is found in the cache memory, IMMEDIATELY it is accessed.

Right option is (b) RDRAM

To ELABORATE: The Rambus RAM can TRANSFER up to 1.6 BILLION bytes per SECOND. It POSSESSES RAM controller, a bus which connects the microprocessor and the device, and random access memory.

Right answer is (d) FPGA

The best explanation: Field programmable GATE ARRAYS are a type of multi-core ARCHITECTURE WHOSE hardware function can be PROGRAMMED by using hardware design tools.

The CORRECT option is (a) burst EDO DRAM

The explanation is: The burst EDO DRAM is evolved from the EDO DRAM and it can access four memory ADDRESSES in one burst. It also SUPPORTS pipeline stages which allow the PAGE access cycle into two parts.

Right CHOICE is (a) dout pin

Easiest explanation: In the basic DRAM interfacing, the higher order bits asserts the RAS SIGNAL and the LOWER order bits asserts the CAS signal. When the access got expired, the data appears on the dout pin and is latched by the PROCESSOR.

The correct option is (b) HIDDEN refresh

Best explanation: In the hidden refresh, the refresh cycle is added to the end of a normal READ cycle. The RAS signal goes high and is then asserted low. At the end of the read cycle, the CAS is still asserted. This is similar to the CBR MECHANISM, that is, toggling of the RAS signal at the end of the read cycle starts a CBR refresh cycle.

Right answer is (d) Apple II PERSONAL computer

For explanation: The Apple II personal computer has a particular memory configuration, periodically the DRAM GETS BLOCKED and is used for video memory accessing to update the SCREEN which can refresh the DRAM.