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Correct answer is (a) twice of NORMAL access

For EXPLANATION: Each of the refresh cycles is approximately as twice as the length of the normal access, for example, a 70ns DRAM has a refresh CYCLE TIME of 130ns.

Correct option is (d) 3.3V

To explain I would SAY: For INCREASING the speed and reducing the power consumption, it is necessary to reduce the power supply. Today’s CPUs and memories have 3.3V supply or even lower instead of the signal level from 0 to 5V. DIMMS are described by its VOLTAGE, speed, and MEMORY type respectively as 3.3V 133MHz SDRAM DIMM.

Right answer is (a) CMOS

For explanation: CMOS is complementary METAL OXIDE semiconductor which is used by MAC and IBM PC as storage element because it contains configuration data of SRAM and is battery back-up to ensure that it is powered up when the computer is SWITCHED off.

Correct choice is (a) M68000

For EXPLANATION I WOULD say: The M68000 uses MEMORY partitioning by the use of function code or by the COMBINATION of superscalar signals and the Harvard architecture.

Correct choice is (C) cache LINE

To elaborate: The cache line REFERS to the number of consecutive bytes which are associated with each cache entry. The DATA is transferred between the memory and the cache in a PARTICULAR size which is called a cache line.

Correct answer is (B) POINTER

The explanation is: Memory model is defined by a range of memory ADDRESS which is accessible to the program. For example, in the C program, the memory address is stored in the pointer.

Correct CHOICE is (c) Rambus DRAM

For explanation I would say: Rambus DRAM is a synchronous MEMORY developed by Rambus. It can replace SDRAM and is USEFUL in high bandwidth APPLICATIONS.

Right choice is (a) video RAM

The best EXPLANATION: Video RAM is a derivative of DRAM. It FUNCTIONS as a DRAM and has additional functions to access data for video HARDWARE for creating the DISPLAY.

The CORRECT choice is (a) 1T-RAM

To elaborate: 1T-RAM is a pseudo-static RAM which is developed by MoSyS, INC. PROM, EPROM, and EEPROM are non-volatile memories.

The correct choice is (C) 6

For explanation: Six MOSFETs are required for a typical SRAM. Each bit of SRAM is stored in four TRANSISTORS which form TWO cross-coupled inverters.

Correct answer is (b) memory array, comparator, counter

To explain: The cache memory operation is based on the ADDRESS tag, that is, the processor generates the address which is provided to the cache and this cache stores its data with an address tag. The tag is COMPARED with the address, if they did not match, the NEXT tag is checked. If they match, a cache hit occurs, the data is PASSED to the processor. So the basic ELEMENTS required is a memory array, comparator, and a counter.

The correct choice is (b) CBR

The explanation is: CBR that is, CAS before RAS refresh is the ONE which is commonly used. It has low power consumption quality because it does not have ADDRESS bus and the buffers can be switched off. It is worked by using an internal address counter which is STORED on the memory chip itself and this can be INCREMENTED periodically.

The correct answer is (B) DRAM

Best EXPLANATION: DRAM is used in PCs and Embedded systems because of its low COST. SRAM, FLASH memory and EEPROM are more COSTLY than DRAM.

Right choice is (a) address translation

Explanation: The MEMORY MANAGEMENT UNIT handles with PHYSICAL ADDRESSES. Therefore, the virtual or the logical address is first translated to the physical address.

Correct choice is (c) simm

To EXPLAIN I would say: The SIMM is basically a subassembly, not a package. It is a SMALL board which possesses finger connection on the bottom and SUFFICIENT MEMORY on the board in order to MAKE up the required configuration.

Right OPTION is (a) Dr.Fujio Masuoka

The best I can EXPLAIN: FLASH memory is invented by Dr. Fujio Masuoka at Toshiba in the 1980s which are non-volatile memory.

Correct ANSWER is (c) JEDEC

To ELABORATE: The maximum TIME interval between refresh cycle is standardized by JEDEC, Joint Electron Device Engineering Council which is an independent semiconductor engineering trade organization. This standardized JEDEC in DRAM is specified in the MANUFACTURER’s chip specification.

Right ANSWER is (a) size of the cache

To explain: The size of the cache increases, a LARGE amount of DATA can be stored, which can access more data which in TURN increases the hit rate of the cache memory.

Correct CHOICE is (a) hit rate

Explanation: The PROPORTION of accesses of DATA that forms the cache hit, which MEASURES the effectiveness of the cache memory.

Right CHOICE is (a) by 1 organisation

Best explanation: The use of By 1 organisation is declined because of the WIDER data path devices. But it is still USED in parity bit and were used in SIMM memory.

Correct choice is (a) sockets and slots

For explanation I WOULD say: The type of PROCESSOR which connects to a socket on the BOTTOM SURFACE of the chip that connects to the motherboard by Zero Insertion Force Socket. Intel 486 is an EXAMPLE of this type of connection. The processor slot is one which is soldered into a card, which connects to a motherboard by a slot. Example for slot connection is Pentium 3.

The correct answer is (B) 10 microseconds

The best EXPLANATION: The maximum time that the RAS SIGNAL can be asserted during the page mode operation is about 10 microseconds. But this is a major disadvantage for page mode operation, that is, the standard PCs have a maximum time of 15 microseconds for the refresh cycle.

Right choice is (b) page mode

The explanation: In the page mode operation, the row address is provided as NORMAL but the RAS signal is left asserted. This, in turn, selects an internal page WITHIN the DRAM memory where any bit of data can be accessed by placing the column address and ASSERTING CAS.

Correct answer is (c) 4

Explanation: There are four data LINES in the memory and these DIFFERENT organisations of memory and these different organisations of memory are APPARENT when upgrading memory and it ALSO determines how MANY chips are needed.

Right answer is (a) add EXTRA description bit

Explanation: The finer grain protection of memory MANAGEMENT is ACHIEVED by the ADDITION of extra description bit to an address to DECLARE its status. The memory management unit can detect an error if the task attempts to access memory that has not been allocated to it or a certain kind of mismatch occurs.

The correct choice is (c) EXTENDED data out

The explanation is: EDO RAM is a special kind of RANDOM access MEMORY which can improve the time to read from the memory on faster MICROPROCESSORS. The example of such a MICROPROCESSOR is Intel Pentium.

Correct OPTION is (c) shifting the SEGMENT by 4

Easy explanation: The ADDRESS BUS of the 8086 is 20-bit and the data bus is 16-bit in size. So the physical address can be calculated by shifting the segment register by 4 to left and by adding the address bus to it.

Correct choice is (a) 4ns

Easy EXPLANATION: SRAM access data in APPROXIMATELY 4ns because of its flip-flop arrangement of TRANSISTORS whereas the data access time in DRAM is approximately 60ns since it has a single capacitor for one-bit storage.

Right choice is (b) CAPACITOR

The EXPLANATION: DRAM uses a small capacitor whose voltage represents a binary zero which is used as a storage element in DRAM in which a SINGLE transistor cell is used to STORE each bit of DATA.

Correct choice is (a) magnetic core memory

Easy explanation: The early FORM of non-volatile memory is KNOWN as magnetic core memory in which the FERROMAGNETIC RING was magnetised to STORE data.

Correct choice is (d) DEBUGGING

Easiest explanation: Debugging in software refresh is very difficult to perform because they MAY STOP the REFRESHING and if the refreshing is stopped, the contents get lost.

Right choice is (a) RAS

The explanation: The row ADDRESS is PLACED on the address BUS and the column address is held off which generates the recycle address. The address generation is DONE by an external hardware CONTROLLER.

The correct ANSWER is (d) Memory PARTITIONING

Explanation: The memory partitioning provides stability to the MULTITASKING system so that the errors WITHIN one TASK will not corrupt the other tasks.

Right CHOICE is (a) single in-line memory module

To explain I would say: SIMM is single in-line memory module is a kind of memory module, which contains random ACCESS memory used in computers of the early 1980S and 1990S.

The correct option is (c) Shifters

The best I can explain: The MEMORY ARRAYS are basically divided into THREE which are RANDOM access memory, serial access memory, and content address memory. Serial access memory is divided into two, theses are shifters and queues.

Right choice is (c) direct mapped cache

The EXPLANATION is: The direct mapped cache has the advantage of allowing a simple and FAST SPECULATIVE EXECUTION.

Correct choice is (b) set associativity

For explanation: The set associativity is a CRITERION which DESCRIBES the number of cache entries which could POSSIBLY contain the REQUIRED DATA.

The correct CHOICE is (a) by 4 organisation

Explanation: By 1 organisation is replaced with By 4 organisation because of its REDUCED address BUS and complexity.

Right choice is (b) by 16 organisation

Easy explanation: The wider memories support 16-bits because it can integrate more NUMBER of the interface LOGIC so that the time consumed by the latches and buffers removes the memory access thus ALLOWING the SLOWER parts to be used in wait state free designs.

The correct choice is (a) 64 Kb

For explanation I WOULD say: The 8086 processor have a 64 Kbytes cache, BEYOND this size, the cost will be extremely high.

Right answer is (c) READ cycle

For EXPLANATION I WOULD say: The read cycle in the DRAM INTERFACING is larger than the ACCESS time because of the precharge time.

Right answer is (C) 15 MICROSECONDS

To explain I would say: The memory refresh is performed every 15 microseconds in order to remain COMPATIBLE.

The correct choice is (a) refresh cycle

Explanation: The DRAM needs to be periodically refreshed and the very BASIC technique is a special refresh cycle, during these CYCLES no other access is permitted. The whole chip is refreshed WITHIN a particular time period otherwise, the data will be lost.