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Correct choice is (a) SRAM

To explain I would say: The low POWER consumption makes SRAM easily CONVERTIBLE to non-volatile memory, by ADDING a small battery it can retain its data even when the MAIN power is lost.

Correct CHOICE is (a) number of transistors

For explanation I would SAY: The CHIP capacity is DEPENDENT on the number of transistors which can be fabricated on the SILICON, and DRAM offers more storage capacity than SRAM.

Correct choice is (a) DRAM

The explanation is: DRAM is highly denser and cheaper because it only uses a single capacitor for STORING ONE BIT.

Correct OPTION is (b) DRAM

The explanation is: Both SRAM and DRAM are volatile memories and flash MEMORY and EPROM are non-volatile memories. DRAM has a storage element as a CAPACITOR whose CHARGE loses gradually thereby losing data.

Right option is (d) ROM

For EXPLANATION I would say: The BASIC non-volatile memory is ROM or mask ROM, and the CONTENT of ROM is fixed in the chip which is useful in FIRMWARE programs for booting up the SYSTEM.

Right answer is (b) distributed refresh

To explain I WOULD say: Most of the system uses the distributed method and depending on the SIZE of the time critical code, the NUMBER of refresh cycles can be CALCULATED.

The correct choice is (c) software refresh

The explanation is: The software refresh performs the action by using a ROUTINE to PERIODICALLY cycle through the memory and REFRESHES. It USES a timer in the program generating an interrupt. This interrupt performs the REFRESHING part in the DRAM.

Correct choice is (b) 0.2ms

For explanation I would say: A 4M by 1 DRAM have 1024 REFRESH cycles. Bursting delay will be 0.2ms that are, the worst case delay is 1024 times larger than that of the SINGLE refresh cycle. The distributed delay is about 170ns.

Correct answer is (d) Dual in-line

To EXPLAIN: The dual-in-line package CONSISTS of two lines of legs on both sides of the plastic or ceramic. Most commonly used are BIOS EPROMs, DRAM and SRAM.

Right choice is (a) DRAM

For EXPLANATION I WOULD say: The signals in address bus are MULTIPLEXED with DRAM non-multiplexed with SRAM.

The correct choice is (c) SIP

To elaborate: The SINGLE-in-line package is the same as that of SIMM, in which the finger connections are REPLACED by a single ROW of pins. SIP took the popularity of SIMM but nowadays it is rarely seen.

Right choice is (a) Non-volatile SRAM

To explain I would say: Random ACCESS Memory is the PRIMARY storage which can access data only when it is powered up. But non-volatile SRAM can access data even when the power supply is lost. It is used in many APPLICATIONS like networking, aerospace ETC.

Right answer is (b) Cache memory

To explain: The cache memory is a small random access memory which is FASTER than a normal RAM. It has a direct connection with the CPU OTHERWISE, there will be a separate bus for ACCESSING data. The processor will check whether the COPY of the required data is present in the cache memory if so it will access the data from the cache memory.

Correct choice is (b) EDO DRAM

For explanation I would say: The EDODRAM is ALSO KNOWN as HYPER page mode enable DRAM because of the faster page mode operation ALONG with some additional FEATURES.

Correct option is (C) PAGE interleaving

Easy EXPLANATION: The accessing of data outside the page boundary can cause missing of PAGES in the page mode OPERATION. So a program has to operate for frequently accessing data thereby, increasing the efficiency in the page selection. One such mode is the page interleaving mode in which the memory is divided into different banks, depending on the number of memories installed.

Correct option is (b) M68000

The best explanation: The M68000 family has a 16 Mbyte ADDRESSING range. The POWERPC family has a LARGER 4 Gbyte range and the DSP56000 has a 128-kilo word ADDRESS space.

Correct option is (C) by refresh cycle and refresh time

The EXPLANATION is: The time required for refreshing the whole chip is known as refresh time. The number of access NEEDED to complete refresh is CALLED as the number of cycles. The number of cycles divided by the refresh time GIVES the refresh rate.

The correct CHOICE is (d) NXP Semiconductor

To elaborate: TriMedia is a VLIW PROCESSOR from NXP Semiconductor in the Netherlands. It possesses a HARVARD architecture CPU for video and audio APPLICATIONS.

Right choice is (c) to select a location within the MEMORY chip

For explanation I would say: ADDRESS bus is used to choose a particular location in the memory chip. DATA bus is used to provide data to and from the chip. Chip select SIGNALS are used to select a particular chip within the memory.